Samsung S3C6400X User Manual page 832

S3C6400X RISC MICROPROCESSOR
CORE INTERRUPT REGISTER (GINTSTS)
This register interrupts the application for system-level events in the current mode of operation (Device mode or
Host mode).
Register Address
GINTSTS 0x7C00_0014
GINTSTS
WkUpInt
SessReqInt
DisconnInt
ConIDStsChng
PTxFEmp
HChInt
PrtInt
reset for proper operation.
R/W
R/W
Bit R/W
[31] R_SS_ Resume/Remote Wakeup Detected Interrupt
WC In Device mode, this interrupt is asserted when a
resume is detected on the USB. In Host mode, this
interrupt is asserted when a remote wakeup is
detected on the USB.
[30] R_SS_ Session Request/New Session Detected Interrupt
WC In Host mode, this interrupt is asserted when a
session request is detected from the device. In
Device mode, this interrupt is asserted when the
b_valid signal goes high.
[29] R_SS_ Disconnect Detected Interrupt
WC Asserted when a device disconnect is detected.
[28] R_SS_ Connector ID Status Change
WC The core sets this bit when there is a change in
connector ID status.
[27] Reserved
[26] RO Periodic TxFIFO Empty
Asserted when the Periodic Transmit FIFO is either
half or completely empty and there is space for at
least one entry to be written in the Periodic Request
Queue. The half or completely empty status is
determined by the Periodic TxFIFO Empty Level bit
in the Core AHB Configuration register.
[25] RO Host Channels Interrupt
The core sets this bit to indicate that an interrupt is
pending on one of the channels of the core (in Host
mode). The application must read the Host All
Channels Interrupt (HAINT) register to determine the
exact number of the channel on which the interrupt
occurred, and then read the corresponding Host
Channel-n Interrupt (HCINTn) register to determine
the exact cause of the interrupt. The application
must clear the appropriate status bit in the HCINTn
register to clear this bit.
[24] RO Host Port Interrupt
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Core Interrupt Register
Description
USB2.0 HS OTG
Reset Value
32 bits
Initial State
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
26-25