Samsung S3C6400X User Manual page 858

S3C6400X RISC MICROPROCESSOR
EnumSpd
SuspSts
DEVICE IN ENDPOINT COMMON INTERRUPT MASK REGISTER (DIEPMSK)
This register works with each of the Device IN Endpoint Interrupt registers for all endpoints to generate an
interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked
by writing to the corresponding bit in this register. Status bits are masked by default.
· Mask interrupt : 1'b0
· Unmask interrupt : 1'b1
Register Address
DIEPMSK 0x7C00_0810
DIEPMSK
INEPNakEffMsk
INTknEPMisMsk
INTknTXFEmpMsk
TimeOUTMsk
AHBErrMsk
EPDisbldMsk
XferComplMsk
asserted due to an erratic error, the application can
only perform a soft disconnect recover.
[2:1] RO Enumerated Speed
Indicates the speed at which the OTG core has
come up after speed detection through a chirp
sequence.
· 2'b00 : High speed (PHY clock is 30 Mhz or 60
Mhz)
· 2'b01 : Full speed (PHY clock is 30 Mhz or 60 Mhz)
· 2'b10 : Low speed (PHY clock is 6 Mhz).
· 2'b11 : Full speed (PHY clock is 48 Mhz).
Low speed is not supported for devices using a
UTMI+ PHY.
[0] RO Suspend Status
In device mode, this bit is set as long as a Suspend
condition is detected on the USB. The core enters
the Suspended state when there is no activity on the
line_state signal for an extended period of time. The
core comes out of the suspend:
· When there is any activity on the line_state signal
· When the application writes to the Remote Wakeup
Signaling bit in the Device Control register.
R/W
R/W
Bit R/W
[31:7] Reserved
[6] R_W IN Endpoint NAK Effective Mask
[5] R_W IN Token received with EP Mismatch Mask
[4] R_W IN Token received with TxFIFO Empty mask
[3] R_W Timeout Condition Mask
[2] R_W AHB Error Mask
[1] R_W Endpoint Disabled Interrupt Mask
[0] R_W Transfer Completed Interrupt Mask
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Device IN Endpoint Common Interrupt Mask
Description
USB2.0 HS OTG
2'h0
1'b0
Reset Value
32 bits
Initial State
25'h0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
26-51