Samsung S3C6400X User Manual page 117

S3C6400X RISC MICROPROCESSOR
T_RC REGISTER
Register
P0T_RC 0x7E000024
P1T_RC 0x7E001024
PnT_RC Bit
[31:4]
t_RC [3:0]
T_RCD REGISTER
Register
P0T_RCD 0x7E000028
P1T_RCD 0x7E001028
PnT_RCD Bit
[31:6]
scheduled_RCD [5:3]
t_RCD [2:0]
T_RFC REGISTER
Register
P0T_RFC 0x7E00002C
P1T_RFC 0x7E00102C
PnT_RFC Bit
[31:10]
scheduled_RFC [9:5]
t_RFC [4:0]
T_RP REGISTER
Register
P0T_RP 0x7E000030
P1T_RP 0x7E001030
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set Active bank x to Active bank x delay in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the RAS to CAS minimum delay in aclk cycles -3.
Set the RAS to CAS minimum delay in memory clock cycles
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the autorefresh command time in aclk cycles -3.
Set the autorefresh command time in memory clock cycles
Address R/W
R/W
R/W
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
16-bit DRAM controller t_RC register
32-bit DRAM controller t_RC register
Description
Description
16-bit DRAM controller t_RCD register
32-bit DRAM controller t_RCD register
Description
Description
16-bit DRAM controller t_RFC register
32-bit DRAM controller t_RFC register
Description
Description
16-bit DRAM controller t_RP register
32-bit DRAM controller t_RP register
DRAM CONTROLLER
Reset Value
0xB
0xB
Initial State
0xB
Reset Value
0x1D
0x1D
Initial State
011
101
Reset Value
0x212
0x212
Initial State
0x10
0x12
Reset Value
0x1D
0x1D
5-11