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MODEM INTERFACE
Timing Diagram
Parameter
t
AVWR
t
CSVWR
t
AWR
t
WR
t
DSUWR
t
DHWR
23-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XhiADR
XhiCSn
t
AWR
XhiWEn
XhiDATA
Figure 23-5 Modem interface write timing diagram
Table 23-2 Modem interface write timing
Description
Address valid to address invalid
Chip select active
Address valid to write active
Write active
Write data setup
Write data hold
S3C6400X
t
AVWR
t
CSVWR
t
WR
t
t
DSUWR
DHWR
Min (ns)
Max (ns)
16 ns
16 ns
4 ns
8 ns
8 ns
4 ns
RISC MICROPROCESSOR
Notes
-
-
-
-
-
-
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