Samsung S3C6400X User Manual page 47

SYSTEM CONTROLLER
Control bus priority
FUNCTIONAL DESCRIPTION
This section describes the functionality of S3C6400X system controller. It covers the clock architecture, reset
scheme, and power management modes.
HARDWARE ARCHITECTURE
Figure 3-1 shows S3C6400X block diagram. S3C6400X consists of ARM1176 processor, several media co-
processors and various peripheral IP's. ARM1176 processor connected to several memory controllers through 64-
bit AXI-bus to meet bandwidth requirements. Media co-processors, which include MFC (Multi-Format Codec),
JPEG, Camera interface, TV encoder and etc, are divided into five power domains. The five power domain can be
controlled independently to reduce unwanted power consumption when the IP's are not required for an application
program.
DOMAIN-V DOMAIN-I
JPEG
MFC
HS
ARM1176
MMC0
SYSCON WDT
GPIO HSI Tx
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-2
Specifications and information herein are subject to change without notice.
DOMAIN-P
Cam. TV
2D
I/F Enc.
AHB-I AHB-P
DOMAIN-X
AHB-X
HS HS USB
MMC1 MMC2 OTG
VIC TZIC
PWM UART PCM0
HSI Rx SPI0 SPI1
Figure 3-1. S3C6400X block diagram
DOMAIN-F
Scaler ROT POST LCD
AHB-F
AXI (64b)
DOMAIN-T
AHB-T0 AHB-M0
Indire
Direct
USB ct
Host DMA0 DMA1
Host Host
IF
IF
AHB-T1 AHB-M1
AXI (32b)
APB (32b)
PCM1 IrDA TSADC
IIS0 IIS1
S3C6400X RISC MICROPROCESSOR
MEMSYS
NF Con.
SROM
OneNAND
DMC1 DMC0
CF Con.
AHB
DOMAIN-M DOMAIN-S
AHB-S0
SDMA SDMA
0 1
AHB-S1
KeyPAD RTC
IIC AC97 TZPC
ROM
AHB
Security
System
ALIVE
S-Key