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S3C6400 RISC MICROPROCESSOR
Channel configuration register, DMACCxConfiguration
The eight DMACCxConfiguration registers are read/write and are used to configure the DMA channel. The registers
are not updated when a new LLI is requested.
Table 11-24 shows the bit assignment of a DMACCxConfiguration register.
DMACCxConfiguration
H
A
L
ITC
IE
FlowCntrl
Reserved
(OneNandModeDst)
DestPeripheral
Reserved
(OneNandModeSrc)
Table 11-24. Bit Assignment of DMACCxConfiguration register
Bits
Type
Function
Halt:
[18]
R/W
0 = allow DMA requests
1 = ignore further source DMA requests.
The contents of the channels FIFO are drained. This value can be used
with the Active and Channel Enable bits to cleanly disable a DMA
channel.
Active:
[17]
R
0 = there is no data in the FIFO of the channel
1 = the FIFO of the channel has data.
This value can be used with the Halt and Channel Enable bits to cleanly
disable a DMA channel.
[16]
R/W
Lock. When set this bit enables locked transfers.
Terminal count interrupt mask. When cleared this bit masks out the
[15]
R/W
terminal count interrupt of the relevant channel.
[14]
R/W
Interrupt error mask. When cleared this bit masks out the error interrupt
of the relevant channel.
[13:11]
R/W
Flow control and transfer type. This value is used to indicate the flow
controller and transfer type. The supported flow controller is only the
DMA controller. The transfer type can be memory-to-memory, memory-
to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.
Reserved, must be written as zero, and masked on read.
[10]
R/W
For channel 3 of DMAC0 and SDMAC0, this bit is used to support page-
write features for OneNAND Controller. If this bit is set to 1 and the
destination address points the address field of OneNAND Controller,
destination address increment setting can support 01 command of
OneNAND Controller.
To be sure, when this bit is set to one, D should be "AHB master 1", DI
should be "increment", DWidth should be "word", and DBSize should be
the multiple of four.
Destination peripheral. This value selects the DMA destination request
[9:6]
R/W
peripheral.
This field is ignored if the destination of the transfer is to memory.
Reserved, must be written as zero, masked on read.
[5]
R/W
For channel 3 of DMAC0 and SDMAC0, this bit is used to support page-
read features for OneNAND Controller. If this bit is set to one and the
source address points the address field of OneNAND Controller, source
address increment setting can support 01 command of OneNAND
Controller.
To be sure, when this bit is set to one, S should be "AHB master 1", SI
should be "increment", SWidth should be "word", and SBSize should be
the multiple of four.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DMA
11-25
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