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FIMV-MFC V1.0
MULTI-FORMAT
CODEC
VIDEO
For example, two processes (MPEG4 Decoder, H.264 Encoder) run simultaneously (full duplex case). If host
executes ENC_PIC_RUN command after DEC_PIC_RUN command, BIT processor needs H.264 encoding code
image to execute H.264 encoding a picture, therefore it loads automatically H.264 encoding code image from
SDRAM (context switching). For the initial BIT processor executing (initial start after hardware reset), initial
booting code image must be downloaded directly by host. Before executing the BIT processor by set [CodeRun]
register, host must directly downloads booting code image (some amount of uppermost part of code image) to the
lowest code memory (address 0) by set [CodeDownLoad] register.
The total byte size of code image of current version of BIT firmware is 80 KB (40K words) and the booting code
image is 1024 byte (512 words).
Bit Stream Buffer management
External bit stream buffer resides in SDRAM and is composed of ring buffer. The start address of ring buffer and
buffer size must be written by host to BIT processor. The current read or write address of ring buffer is
automatically wrapped-around.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-99
Specifications and information herein are subject to change without notice.
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