Samsung S3C6400X User Manual page 993

IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER
Register
IICSTAT 0x7F004004
IICSTAT
Mode selection
Busy signal status /
START STOP condition
Serial output
Arbitration status flag
Address-as-slave status
flag
Address zero status flag
Last-received bit status flag
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
30-12
Specifications and information herein are subject to change without notice.
Address R/W
R/W
Bit
[7:6] IIC-bus master/slave Tx/Rx mode select bits.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
[5] IIC-Bus busy signal status bit.
0: read) Not busy (when read)
write) STOP signal generation
1: read) Busy (when read)
write) START signal generation.
[4] IIC-bus data output enable/disable bit.
0: Disable Rx/Tx,
[3] IIC-bus arbitration procedure status flag bit.
0: Bus arbitration successful
1: Bus arbitration failed during serial I/O
[2] IIC-bus address-as-slave status flag bit.
0: Cleared after reading of IICSTAT register
1: Received slave address matches the address
value in the IICADD
[1] IIC-bus address zero status flag bit.
0: Cleared when START/STOP condition was
detected
1: Received slave address is 00000000b.
[0] IIC-bus last-received bit status flag bit.
0: Last-received bit is 0 (ACK was received).
1: Last-received bit is 1 (ACK was not received).
Description
IIC-Bus control/status register
Description
The data in IICDS will be transferred
automatically just after the start signal.
1: Enable Rx/Tx
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
0x0
00
0
0
0
0
0
0