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S3C6400X RISC MICROPROCESSOR
RX MODULE I/O LIST
Name
APB Interface Signals (Rx)
PCLK
PRESETn
PADDR
PWRITE
PRDATA
PWDATA
PSEL
PENABLE
Interrupt & DMA Request Signals
INT_MIPI_RX
DMAREQ_RX
DMAREQ_CLR
SYSCON wakeup Signals (Rx)
MIPI_WAKEUP
wakeup_enn
MIPI HSI interface Signals (Rx)
RX_DATA
RX_FLAG
RX_WAKE
RX_READY
Scan Test mode
STMODE
If DMA request enable bit at interrupt & DMA request mask register is 'enable' and DMA request threshold value
bits at configuration register0 is set(0x00~0x11), Rx module will request DMA operation when the number of data
in Rx FIFO is more than threshold value in configuration register0.
# bits
I/O
1
I
APB bus clock
1
I
APB bus reset
3
I
APB bus address
1
I
APB bus write
32
O
APB bus read data
32
I
APB bus write data
1
I
APB module select
1
I
APB bus trans. It must be connected "HTRANS_bus[1]".
1
O
Interrupt request
1
O
DMA request
1
I
DMA request clearing signal from DMAC
1
O
Wake-up signal for SYSCON
1
O
Wake-up signal enable for FPC
1
I
MIPI HSI data line
1
I
MIPI HSI flag line
1
I
MIPI HSI wake up line from the other side Tx
1
O
MIPI HSI ready line to the other side Tx
1
I
Scan Test mode
Table 28-2 RX I/O Description
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Function
MIPI HSI
28-7
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