Samsung S3C6400X User Manual page 322

DMA
SrcPeripheral
E
Table 11-25 describes the bit values of the three flow control and transfer type bits.
Bits value Transfer type
000 Memory to memory
001 Memory to peripheral
010 Peripheral to memory
011 Source peripheral to destination
peripheral
100~111 reserved
Preliminary product information describe products that are in development,
11-26
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Source peripheral. This value selects the DMA source request
[4:1] R/W
peripheral.
This field is ignored if the source of the transfer is from memory.
Channel enable. Reading this bit indicates whether a channel is currently
[0] R/W
enabled or disabled:
0 = channel disabled
1 = channel enabled.
The Channel Enable bit status can also be found by reading the
DMACEnbldChns register.
A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the
current AHB transfer (if one is in progress) to complete and the channel
is then disabled. Any data in the channels FIFO is lost. Restarting the
channel by simply setting the Channel Enable bit has unpredictable
effects and the channel must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the
last LLI is reached or if a channel error is encountered.
If a channel has to be disabled without losing data in a channels FIFO
the Halt bit must be set so that further DMA requests are ignored. The
Active bit must then be polled until it reaches 0, indicating that there is no
data left in the channels FIFO. Finally the Channel Enable bit can be
cleared.
Table 11-25. Flow control and transfer type bits
S3C6400 RISC MICROPROCESSOR
Controller
DMA
DMA
DMA
DMA