Samsung S3C6400X User Manual page 112

DRAM CONTROLLER
REGISTER DESCRIPTION
DRAM CONTROLLER STATUS REGISTER
Register
P0MEMSTAT 0x7E000000
P1MEMSTAT 0x7E001000
PnMEMSTAT Bit
Reserved [31:14]
Memory banks [13:12]
Exclusive
[11:10]
monitors
Reserved [9]
Memory chips [8:7]
Memory type [6:4]
Memory width [3:2]
Controller status [1:0]
DRAM CONTROLLER COMMAND REGISTER
Register
P0MEMCCMD 0x7E000004
P1MEMCCMD 0x7E001004
PnMEMCCMD Bit
[31:3]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-6
Specifications and information herein are subject to change without notice.
Address R/W
R
R
Read undefined.
The maximum number of banks that DRAM controller supports on
each chip.
00 = 4 banks
The number of exclusive access monitor resources
10 = 2 monitors
Read always zero.
The maximum number of different chip selects that DRAM
controller can supports:
11 = 4 chips
However, S3C6400X uses only two chip select signals per DRAM
controller.
The type of SDRAM that DRAM controller supports:
100 = Support SDR SDRAM (normal or mobile) and DDR SDRAM
(normal or mobile)
The width of the external memory
00 = 16-bit 01 = 32-bit
The status of the DRAM controller
00 = Config. 01 = Ready
Address R/W
W
W
Undefined. Write as Zero
Description
16-bit DRAM controller status register
32-bit DRAM controller status register
Description
10 = 64-bit
10 = Paused
Description
16-bit DRAM controller command register
32-bit DRAM controller command register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
11 = reserved
11 = Low-Power
Reset Value
Initial State
0xAB0
0xAB4
00
10
0
11
100
00 / 01
00