Samsung S3C6400X User Manual page 843

USB2.0 HS OTG
DPTxFStAddr
HOST MODE REGISTERS
These registers affect the operation of the core in the Host mode. Host mode registers must not be accessed in
Device mode, as the results are undefined. Host Mode registers can be categorized as follows :
· Host Global registers
· Host Port Control and Status registers
· Host Channel-Specific registers
HOST GLOBAL REGISTERS
HOST CONFIGURATION REGISTER (HCFG)
This register configures the core after power-on. Do not make changes to this register after initializing the host.
Register Address
HCFG 0x7C00_0400
HCFG
FSLSSupp
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-36
Specifications and information herein are subject to change without notice.
R_W
[15:0] Device Periodic TxFIFO RAM Start Address
Holds the start address in the RAM for this periodic
FIFO.
The power-on reset value of this register is sum of
the Largest Rx Data FIFO Depth, Largest Non-
Periodic Tx Data FIFO Depth, and all lower
numbered Largest Device Mode Periodic Tx Data
FIFOn Depth specified.
If you have programmed new values for the
RxFIFO, Non-Periodic TxFIFO, or device Periodic
TxFIFOs you can write their sum in this field.
Programmed values must not exceed the power-on
value set.
R/W
R/W
Bit R/W
[31:3] Reserved
[2] R_W FS- and LS- Only Support
The application uses this bit to control the core's
enumeration speed. Using this bit, the application
can make the core enumerate as a FS host, even if
the connected device supports HS traffic. Do not
Description
OTG Control and Status Register
Description
S3C6400X RISC MICROPROCESSOR
n :1 (16'h3000)
n :2 (16'h3300)
n :3 (16'h3600)
n :4 (16'h3900)
n :5 (16'h3C00)
n :6 (16'h3F00)
n :7 (16'h4200)
n :8 (16'h4500)
n :9 (16'h4800)
n :10 (16'h4B00)
n :11 (16'h4E00)
n :12 (16'h5100)
n :13 (16'h5400)
n :14 (16'h5700)
n :15 (16'h5A00)
Reset Value
Initial State
32 bits
29'h0
1'b0