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DISPLAY CONTROLLER
Window 1 Position Control C Register
Register
VIDOSD1C
VIDOSD1C
-
ALPHA0_R
ALPHA0_G
ALPHA0_B
ALPHA1_R
ALPHA1_G
ALPHA1_B
Window 1 Position Control D Register
Register
VIDOSD1D
VIDOSD1D
-
-
OSDSIZE
Window 2 Position Control A Register
Register
VIDOSD2A
VIDOSD2A
OSD_LeftTopX_F
OSD_LeftTopY_F
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-50
Specifications and information herein are subject to change without notice.
Address
R/W
0x77100058
R/W
Bit
[24]
Reserved
[23:20]
Red Alpha value(case AEN == 0)
[19:16]
Green Alpha value(case AEN == 0)
[15:12]
Blue Alpha value(case AEN == 0)
[11:8]
Red Alpha value(case AEN == 1)
[7:4]
Green Alpha value(case AEN == 1)
[3:0]
Blue Alpha value(case AEN == 1)
Address
R/W
0x7710005C
R/W
Bit
[25]
Reserved
[24]
Reserved
[23:0]
Window Size
Eq. Height * Width(Number of Word)
Note. Set filed value for YUV if (TV Encoder IF)
Address
R/W
0x77100060
R/W
Bit
[21:11]
Horizontal screen coordinate for left top pixel of OSD image
[10:0]
Vertical screen coordinate for left top pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
Description
Video Window 1's alpha control register
Description
Description
Video Window 0's Size control register
Description
Description
Video Window 2's position control register
Description
S3C6400X RISC MICROPROCESSOR
Reset
Value
0x0
initial
state
0
0
0
0
0
0
0
Reset
Value
0x0
initial
state
0
0
0
Reset
Value
0x0
initial
state
0
0
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