Samsung S3C6400X User Manual page 319

S3C6400 RISC MICROPROCESSOR
Table 11-19. Bit Assignment of DMACCxControl register (continued)
DMACCxControl Bits
S [24]
Dwidth [23:21]
SWidth [20:18]
DBSize [17:15]
SBSize [14:12]
Reserved [11:0]
Table 11-20. Source or destination burst size
Bit value of DBSize or
SBSize
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
AHB access information is provided to the source and destination peripherals when a transfer occurs. The transfer
information is provided by programming the DMA channel (the Prot bit of the DMACCxControl register, and the Lock
bit of the DMACCxConfiguration register). These bits are programmed by software and peripherals can use this
information if necessary. Three bits of information are provided, and Table 11-22 shows the purpose of the three
protection bits.
Type Function
Source AHB master select:
R/W
0 = AHB master 1 (AXI_SPINE) selected for the source transfer
1 = AHB master 2 (AXI_PERI) selected for the source transfer.
Destination transfer width. Transfers wider than the AHB master bus width
R/W
are illegal.
The source and destination widths can be different from each other. The
hardware automatically packs and unpacks the data as required.
Source transfer width. Transfers wider than the AHB master bus width are
R/W
illegal.
The source and destination widths can be different from each other. The
hardware automatically packs and unpacks the data as required.
Destination burst size. Indicates the number of transfers which make up a
R/W
destination burst transfer request. This value must be set to the burst size
of the destination peripheral, or if the destination is memory, to the
memory boundary size. The burst size is the amount of data that is
transferred when the DMACxBREQ signal goes active in the destination
peripheral.
The burst size is not related to the AHB HBURST signal.
Source burst size. Indicates the number of transfers which make up a
R/W
source burst. This value must be set to the burst size of the source
peripheral, or if the source is memory, to the memory boundary size. The
burst size is the amount of data that is transferred when the
DMACxBREQ signal goes active in the source peripheral.
The burst size is not related to the AHB HBURST signal.
Reserved
R
Source or destination burst
transfer request size
1
4
8
16
32
64
128
256
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 11-21. Source or destination transfer width
Bit value of SWidth or
DWidth
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
DMA
Source or destination
width
Byte (9-bit)
Half word (16-bit)
Word (32-bit)
Reserved
Reserved
Reserved
Reserved
Reserved
11-23