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DISPLAY CONTROLLER
VTIME CONTROLLER OPERATION
VTIME is mainly divided into to blocks. One is VTIME_RGB_TV for RGB interface and TV Encoder Interface
timing control. The other is for I80 CPU interface timing control.
RGB Interface Controller
The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK
signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2
registers in the VSFR register. Based on these programmable configurations of the display control registers in
VSFR, the VTIME module can generate the programmable control signals suitable for the support of many
different types of display device.
The RGB_VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The
RGB_VSYNC and RGB_HSYNC pulse generation is controlled by the configuration of both the HOZVAL field and
the LINEVAL registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to
the following equations:
HOZVAL = (Horizontal display size) -1
LINEVAL = (Vertical display size) –1
The rate of RGB_VCLK signal can be controlled by the CLKVAL field in the VIDCON0 register. The table below
defines the relationship of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.
RGB_VCLK (Hz) =HCLK/ (CLKVAL+1) where CLKVAL >= 1
Table 14-4. Relation between VCLK and CLKVAL (TFT, Freq. of Video Clock Source=60MHz)
CLKVAL
2
3
:
63
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-24
Specifications and information herein are subject to change without notice.
60MHz/X
60 MHz/3
60 MHz/4
:
60 MHz/64
S3C6400X RISC MICROPROCESSOR
VCLK
20.0 MHz
15.0 MHz
:
937.5 kHz
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