Samsung S3C6400X User Manual page 1051

Real Time Clock
INDIVIDUAL REGISTER DESCRIPTIONS
REAL TIME CLOCK CONTROL (RTCCON) REGISTER
The RTCCON register consists of 9 bits such as the RTCEN. It controls the read/write enable of the BCD SEL,
CNTSEL and CLKRST for testing.
RTCEN bit can control all interfaces between the CPU and the RTC, Therefore it must be set to 1 in an RTC
control routine to enable data read/write after a system reset. Before power off, the RTCEN bit must be cleared
to 0 to prevent inadvertent writing into RTC registers.
Register Address
RTCCON 0x7E005040
RTCCON Bit Description
TICEN [8] Tick timer enable
0 = Disable
Reserved [7:4] Reserved
CLKRST RTC clock count reset.
[3]
0 = No reset,
CNTSEL [2] BCD count select.
0 = Merge BCD counters
1 = Reserved (Separate BCD counters)
CLKSEL [1] BCD clock select.
0 = XTAL 1/2
1 = Reserved (XTAL clock only for test)
RTCEN [0] RTC control enable.
0 = Disable
Note: When RTCEN is enable, BCD time count setting, RTC clock
counter reset and read operation can be performed.
Note:
TIC Counter is enabled / disabled at TICCLK rising edge.
If TICEN is high, TIC counter is updated at TICCLK rising edge
But, if TICEN is low, TIC counter is cleared at TICCLK rising edge.
TICK TIME COUNT REGISTER (TICNT)
Register Address
TICNT 0x57000044
TICNT Bit
TICK TIME [15:0]
COUNT
33-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W Description
R/W RTC control Register
1 = Enable
1 = Reset
15
divided clock
1 = Enable
R/W Description
R/W Tick time count register
Description
16 bit tick time count value
S3C6400
RISC MICROPROCESSOR
Reset Value
0x0
Initial State
0
0
0
0
0
Reset Value
0x0
Initial State
16'b0