Samsung S3C2501X Manuals

Manuals and User Guides for Samsung S3C2501X. We have 1 Samsung S3C2501X manual available for free PDF download: User Manual

Samsung S3C2501X User Manual

Samsung S3C2501X User Manual (465 pages)

32-BIT RISC MICROPROCESSOR

Brand: Samsung | Category: Computer Hardware | Size: 2.14 MB

Table of Contents

Important Notice
2
Table of Contents
3
List of Tables
19
Overview
23
Chapter 1 Product Overview

26
- Overview
  26
- Features
  27
- Block Diagram
  29
- Package Diagram
  30
- Pin Assignment
  31
- Signal Description
  37
- Pad Type
  51
- Special Registers
  52
Chapter 2 Programmer's Model

60
- Overview
  60
- Switching State
  60
  - Entering THUMB State
    60
  - Entering ARM State
    60
- Memory Formats
  61
  - Big-Endian Format
    61
  - Little-Endian Format
    61
- Data Types
  62
- Instruction Length
  62
- Operating Modes
  62
- Registers
  63
- Register Organization in ARM State
  64
- Register Organization in THUMB State
  65
  - The Relationship between ARM and THUMB State Registers
    66
  - Accessing Hi-Registers in THUMB State
    67
- The Program Status Registers
  67
  - The Condition Code Flags
    68
  - The Control Bits
    68
- Exceptions
  70
  - Action on Entering an Exception
    70
  - Action on Leaving an Exception
    70
  - Exception Entry/Exit Summary
    71
  - Fiq
    71
  - Irq
    72
  - Abort
    72
  - Software Interrupt
    73
  - Undefined Instruction
    73
- Exception Vectors
  73
  - Exception Priorities
    74
  - Not All Exceptions Can Occur at Once
    74
- Interrupt Latencies
  75
- Reset
  75
- Introduction for ARM940T
  76
- ARM940T Block Diagram
  77
- About the ARM940T Programmer's Model
  78
  - Data Abort Model
    79
  - Instruction Set Extension Spaces
    79
- ARM940T CP15 Registers
  80
  - CP15 Register Map Summary
    80
Chapter 3 Instruction Set

92
- Instruction Set Summay
  92
  - Format Summary
    92
- ARM Instruction Set Format
  92
  - Instruction Summary
    93
  - The Condition Field
    95
  - Branch and Exchange (BX)
    96
    
    Instruction Cycle Times
    96
    
    Assembler Syntax
    96
    
    Using R15 as an Operand
    96
  - Branch and Branch with Link (B, BL)
    98
    
    The Link Bit
    98
    
    Instruction Cycle Times
    98
- Branch Instructions
  98
  - Assembler Syntax
    99
  - Data Processing
    100
    
    CPSR Flags
    102
    
    Shifts
    103
- ARM Shift Operations
  103
- Arithmetic Shift Right
  103
- Rotate Right
  103
  - Immediate Operand Rotates
    107
  - Writing to R15
    107
  - Using R15 as an Operand
    107
  - Teq, Tst, Cmp and CMN Opcodes
    107
  - Instruction Cycle Times
    108
  - Assembler Syntax
    108
  - PSR Transfer (MRS, MSR)
    110
    
    Operand Restrictions
    110
- PSR Transfer
  110
  - PSR Transfer
    111
  - Instruction Cycle Times
    112
  - Reserved Bits
    112
  - Assembler Syntax
    113
  - Multiply and Multiply-Accumulate (MUL, MLA)
    114
    
    CPSR Flags
    115
    
    Instruction Cycle Times
    115
    
    Assembler Syntax
    115
  - Multiply Long and Multiply-Accumulate Long (Mull,Mlal)
    116
    
    Operand Restrictions
    116
    
    CPSR Flags
    117
    
    Instruction Cycle Times
    117
    
    Assembler Syntax
    118
  - Single Data Transfer (LDR, STR)
    119
    
    Offsets and Auto-Indexing
    120
    
    Shifted Register Offset
    120
    
    Bytes and Words
    120
- Little-Endian Offset Addressing
  121
  - Use of R15
    122
  - Restriction on the Use of Base Register
    122
  - Data Aborts
    122
  - Instruction Cycle Times
    122
  - Assembler Syntax
    123
- Chapter 3 Instruction Set (Continued)
  123
  - Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH)
    125
- Half-Word and Signed Data Transfer with Register Offset
  125
  - Offsets and Auto-Indexing
    126
  - Half-Word Load and Stores
    127
  - Signed Byte and Half-Word Loads
    127
  - Endianness and Byte/Half-Word Selection
    127
  - Use of R15
    128
  - Data Aborts
    128
  - Instruction Cycle Times
    128
  - Assembler Syntax
    129
  - Block Data Transfer (LDM, STM)
    131
    
    The Register List
    131
- Block Data Transfer Instructions
  131
  - Addressing Modes
    132
  - Address Alignment
    132
- Pre-Increment Addressing
  133
  - Use of the S Bit
    134
  - Use of R15 as the Base
    134
  - Inclusion of the Base in the Register List
    135
  - Data Aborts
    135
  - Instruction Cycle Times
    135
  - Assembler Syntax
    136
  - Single Data Swap (SWP)
    138
    
    Bytes and Words
    138
    
    Use of R15
    138
    
    Data Aborts
    139
    
    Instruction Cycle Times
    139
    
    Assembler Syntax
    139
  - Software Interrupt (SWI)
    140
    
    Return from the Supervisor
    140
    
    Comment Field
    140
    
    Instruction Cycle Times
    140
- Software Interrupt Instruction
  140
  - Assembler Syntax
    141
  - Coprocessor Data Operations (CDP)
    142
    
    Coprocessor Instructions
    142
    
    The Coprocessor Fields
    142
- Coprocessor Data Operation Instruction
  142
  - Instruction Cycle Times
    143
  - Assembler Syntax
    143
  - Coprocessor Data Transfers (LDC, STC)
    144
    
    The Coprocessor Fields
    144
- Coprocessor Data Transfer Instructions
  144
  - Addressing Modes
    145
  - Address Alignment
    145
  - Use of R15
    145
  - Data Aborts
    145
  - Instruction Cycle Times
    145
  - Assembler Syntax
    146
- Chapter 3 Instruction Set (Continued)
  146
- Coprocessor Register Transfers (MRC, MCR)
  147
  - The Coprocessor Fields
    147
- Coprocessor Register Transfer Instructions
  147
  - Transfers to R15
    148
  - Transfers from R15
    148
  - Instruction Cycle Times
    148
  - Assembler Syntax
    148
- Undefined Instruction
  149
  - Instruction Cycle Times
    149
  - Assembler Syntax
    149
- Instruction Set Examples
  150
- Thumb Instruction Set Format
  155
  - Format Summary
    155
- THUMB Instruction Set Formats
  155
  - Opcode Summary
    156
- Format 1: Move Shifted Register
  158
  - Operation
    158
  - Instruction Cycle Times
    158
- Format 2: Add/Subtract
  159
  - Operation
    159
  - Instruction Cycle Times
    160
- Format 3: Move/Compare/Add/Subtract Immediate
  161
  - Operations
    161
  - Instruction Cycle Times
    161
- Format 4: ALU Operations
  162
  - Operation
    162
  - Instruction Cycle Times
    163
- Format 5: Hi-Register Operations/Branch Exchange
  164
  - Operation
    164
  - Instruction Cycle Times
    165
  - The Bx Instruction
    165
  - Using R15 as an Operand
    166
- Format 6: PC-Relative Load
  167
  - Operation
    167
  - Instruction Cycle Times
    167
- Format 7: Load/Store with Register Offset
  168
  - Operation
    168
  - Instruction Cycle Times
    169
- Format 8: Load/Store Sign-Extended Byte/Half-Word
  170
  - Operation
    170
  - Instruction Cycle Times
    171
- Chapter 3 Instruction Set (Continued)
  171
- Format 9: Load/Store with Immediate Offset
  172
  - Operation
    172
  - Instruction Cycle Times
    173
- Format 10: Load/Store Half-Word
  174
  - Operation
    174
  - Instruction Cycle Times
    174
- Format 11: SP-Relative Load/Store
  175
  - Operation
    175
  - Instruction Cycle Times
    175
- Format 12: Load Addres
  176
  - Operation
    176
  - Instruction Cycle Times
    177
- Format 13: Add Offset to Stack Pointer
  178
  - Operation
    178
  - Instruction Cycle Times
    178
- Format 14: Push/Pop Registers
  179
  - Operation
    179
  - Instruction Cycle Times
    180
- Format 15: Multiple Load/Store
  181
  - Operation
    181
  - Instruction Cycle Times
    181
- Format 16: Conditional Branch
  182
  - Operation
    182
  - Instruction Cycle Times
    183
- Format 17: Software Interrupt
  184
  - Operation
    184
  - Instruction Cycle Times
    184
- Format 18: Unconditional Branch
  185
  - Operation
    185
- Format 19: Long Branch with Link
  186
  - Operation
    186
  - Instruction Cycle Times
    187
- Instruction Set Examples
  188
Chapter 4 System Configuration

192
- Overview
  192
- Features
  192
- Address Map
  193
- Remap of Memory Space
  194
- External Address Translation
  194
- Arbitration Scheme
  195
- Priority Groups of S3C2501X
  196
- AHB Programmable Priority Registers
  197
  - Problem Solvings with Programmable Round-Robin
    198
- Clock Configuration
  200
- Shows the Clock Generation Logic of the S3C2501X
  205
- System Configuration Special Registers
  206
  - System Configuration Register
    207
  - Product Code and Revision Number Register
    209
  - Clock Control Register
    210
  - Peripheral Clock Disable Register
    211
  - Clock Status Register
    212
  - AHB Bus Master Priority Register
    212
  - Core PLL Control Register
    213
  - System Bus PLL Control Register
    214
  - PHY PLL Control Register
    215
Chapter 5 Memory Controller

216
- Overview
  216
- Features
  217
- Memory Map
  218
- Memory Bank Address Map
  219
- Bus Interface Signals
  220
- Memory Controller Bus Signals
  221
- Endian Modes
  222
- Ext I/O Bank Controller
  228
  - Features
    228
  - External Device Connection
    229
- Bit ROM, SRAM and Flash Basic Connection (8-Bit Memory X 2)
  230
- Bit SRAM Basic Connection
  231
- Bit ROM and Flash Basic Connection
  232
- Bit ROM Basic Connection 2
  233
- Bit SRAM Basic Connection 2
  234
  - ROM & SRAM with Muxed Address & Data Bus Connection
    235
  - Ext. I/O Bank Controller Special Register
    236
- Bncon
  237
- Bank N Control (Bncon) Register Configuration
  239
- Muxed Bus Control (MUXBCON) Register Configuration
  241
- Wait Control (WAITCON) Register Configuration
  243
  - Timing Diagram
    244
- Write Timing Diagram 1
  245
- Read Timing Diagram 2
  246
- Write Timing Diagram 2
  247
- Read after Write at the same Bank (COHDIS = 1)
  248
- Read Timing Diagram (Muxed Bus)
  249
- Write Timing Diagram (Muxed Bus)
  250
- Write Timing Diagram (Newait)
  251
- Write Timing Diagram (Nready)
  252
- SDRAM Controller
  253
  - Features
    253
  - SDRAM Size and Configuration
    254
  - Address Mapping
    257
  - SDRAM Commands
    259
  - External Data Bus Width
    260
  - Merging Write Buffer
    260
  - Self Refresh
    260
  - Basic Operation
    261
  - SDRAM Special Registers
    262
- SDRAM Configuration Register 0
  264
- SDRAM Command Register
  266
- SDRAM Refresh Timer Register
  267
- SDRAM Write Buffer Time-Out Register
  268
  - SDRAM Controller Timing
    269
- Single Read Operation (CAS Latency=3)
  270
- Single Write Operation
  271
- Burst Read Operation (CAS Latency = 2)
  272
- Burst Read Operation (CAS Latency = 3)
  273
- Burst Write Operation
  274
Chapter 6 I C Bus Controller

276
- Overview
  276
- Features
  276
- Functional Description
  277
- I 2 C Concepts
  278
  - Basic Operation
    278
  - General Characteristics
    279
  - Bit Transfers
    279
  - Data Validity
    280
  - Start and Stop Conditions
    280
  - Data Transfer Operations
    281
- Data Transfer Format
  282
  - I 2 C Special Registers
    283
    
    Control Status Register
    283
    
    I 2 C Control Status Register
    284
    
    Shift Buffer Register
    285
    
    Prescaler Register
    285
    
    Prescaler Counter Register
    286
    
    Interrupt Pending Register
    286
Chapter 7 Ethernet Controller

290
- Overview
  290
- Features
  291
- MAC Function Blocks
  292
  - Media Independent Interface (MII)
    292
  - Physical Layer Entity (PHY)
    293
  - Buffered Dma Interface (BDI)
    293
  - The MAC Transmitter Block
    293
  - The MAC Receiver Block
    295
  - Flow Control Block
    296
  - Buffered DMA (BDMA) Overview
    296
- Data Structure of Tx Buffer Descriptor
  299
- Data Structure of Rx Buffer Descriptor
  300
- Data Structure of the Receive Frame
  301
  - Ethernet Controller Special Registers
    302
    
    BDMA Relative Special Register
    304
    
    MAC Relative Special Register
    313
    
    MAC Frame Format
    326
  - Ethernet Operations
    326
- Fields of an Ieee802.3/Ethernet Frame
  327
- CSMA/CD Transmit Operation
  329
- Timing for Transmission Without Collision
  330
- Timing for Transmission with Collision in Preamble
  331
- Receiving Frame Without Error
  332
- CSMA/CD Receive Operation
  333
  - The MII Station Manager
    334
  - Full-Duplex Pause Operations
    335
  - Error Signalling
    337
  - Timing Parameters for MII Transactions
    339
Chapter 8 DES/3DES

340
- Overview
  340
- Feature
  340
- DES/3DES Block Diagram
  341
  - DES/3DES Special Registers
    342
    
    DES/3DES Control Register
    343
    
    DES/3DES Status Register
    344
    
    DES/3DES Interrupt Enable Register
    345
    
    DES/3DES Run Enable Register
    345
    
    DES/3DES Key1 Left/Right Side Register
    345
    
    DES/3DES Key 2 Left/Right Side Register
    346
    
    DES/3DES Key 3 Left Side Register
    346
    
    DES/3DES IV Left/Right Side Register
    346
    
    DES/3DES Input/Output Data FIFO Register
    347
  - DES/3DES Operation
    348
  - Performance Calculation Guide
    349
Chapter 9 GDMA Controller

350
- Overview
  350
- Feature
  350
- GDMA Controller Block Diagram
  351
  - GDMA Special Registers
    352
    
    GDMA Programmable Priority Registers
    353
    
    GDMA Programmable Priority Registers
    354
    
    GDMA Control Registers
    358
- GDMA Control Register
  360
  - GDMA Source/Destination Address Registers
    361
  - GDMA Transfer Count Registers
    362
  - GDMA Run Enable Registers
    363
  - GDMA Interrupt Pending Register
    364
  - GDMA Mode Operation
    365
    
    Software Mode
    365
    
    External GDMA Request Mode
    365
    
    HUART Mode
    365
    
    DES Mode
    366
  - GDMA Function Description
    366
    
    GDMA Transfers
    366
    
    Starting/Ending GDMA Transfers
    366
    
    Data Transfer Modes
    367
  - GDMA Transfer Timing Data
    368
    
    Single and One Data Burst Mode
    369
    
    Single and Four Data Burst Mode
    370
    
    Block and One Data Burst Mode
    371
- Block and Four Data Burst
  372
Chapter 10 Serial I/O (Console UART)

374
- Overview
  374
- Features
  374
- Console UART Block Diagram
  375
  - Console UART Special Registers
    376
    
    Console UART Control Registers
    377
- Console UART Control Register
  379
- Serial I/O Frame Timing Diagram (Normal Console UART)
  392
- Infra-Red Receive Mode Frame Timing Diagram
  393
Chapter 11 Serial I/O (High-Speed UART)

394
Chapter 12 I/O Ports

424
- Overview
  424
- Features
  424
- I/O Port Special Register
  425
  - I/O Port Mode Select Register
    425
- I/O Port Mode Registers 1/2
  426
  - I/O Port Function Control Register
    427
- I/O Function Control Register 1
  428
- I/O Function Control Register 2
  429
Chapter 13 Interrupt Controller

436
- Overview
  436
- Features
  436
- Interrupt Sources
  437
- Interrupt Controller Special Registers
  438
  - Interrupt Mode Registers
    438
- Internal Interrupt Mode Register
  439
  - Interrupt Mask Registers
    440
- Internal Interrupt Mask Register
  441
- External Interrupt Mask Register
  442
  - Interrupt Priority Registers
    443
  - Interrupt Offset Register
    444
  - Interrupt by Priority Register
    447
  - Interrupt Test Register
    447
Chapter 1432 -Bit Timers

448
- Overview
  448
- Interval Mode Operation
  449
- Toggle Mode Operation
  449
- Timer Operation Guidelines
  450
  - Timer Mode Register
    451
  - Timer Mode Register
    452
  - Timer Data Registers
    453
- Timer Count Registers
  454
  - Timer Interrupt Clear Registers
    455
  - Watchdog Timer Register
    456
Chapter 15 Electrical Data

458
- Overview
  458
- Absolute Maximum Ratings
  458
- Recommended Operating Conditions
  458
- DC Electrical Specifications
  459
- AC Electrical Characteristics
  461
Chapter 16 Mechanical Data

464
- Overview
  464
- Mechanical Data
  464
- BGA-2727-AN Package Dimensions
  465

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