Samsung S3C6400X User Manual page 49

SYSTEM CONTROLLER
CLOCK SOURCE SELECTION
Internal clocks will be generated using external clock source as shown in Table 3-1. The OM[4:0] pins determines
the operating mode of S3C6400X when the external reset signal is asserted. As shown in the Table 3-1, the
OM[0] selects the external clock source, i.e., if the OM[0] is 0, the XXTIpll (external crystal) is selected. Otherwise,
XEXTCLK is selected.
OM[4:0]
0000X
0001X
0010X
0011X
0100X
0101X
0110X
0111X
RESERVED
1111X
The operating mode is mainly classified into six categories according to the boot device. The boot device can be
among NAND, SROM, NOR, OneNAND, MODEM, Internal ROM. The additional characteristics can be selected
when the boot device is NAND as shown Table 3-1. When NAND Flash device is used, XSELNAND pin must be
1, whether is used as boot device or storage device. When OneNAND Flash device is used, XSELNAND must be
0, whether it is used as boot device or storage device. When NAND/OneNAND device is not used, XSELNAND
can be 0 or 1.
PHASE LOCKED LOOP (PLL)
Three PLL's within S3C6400X, APLL, MPLL, and EPLL, synchronizes an output signal with a reference input
clock in operating frequency and phase. In this application, it includes the following basic blocks as shown in
Figure 3-3. The Voltage Controlled Oscillator (VCO) generates the output frequency proportional to input DC
voltage. The pre-divider divides the input frequency (FIN) by P. The main divider divides the VCO output
frequency by M, which is input to Phase Frequency Detector (PFD). The post scaler divides the VCO output
frequency by S. The phase difference detector calculates the phase difference and the charge pump increases /
decreases the output voltage. The output clock frequencies of each PLL can be calculated
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-4
Specifications and information herein are subject to change without notice.
Table 3-1. Device operating mode selection at boot-up
Boot Device
AdvFlash=0, AddrCycle=3
AdvFlash=0, AddrCycle=4
NAND
AdvFlash=1, AddrCycle=4
AdvFlash=1, AddrCycle=5
SROM
NOR (26bit)
OneNAND
MODEM
RESERVED
Internal ROM
S3C6400X RISC MICROPROCESSOR
Function
XXTIpll if OM[0] is 0.
-
XEXTCLK if OM[0] is 1.
-
-
-
-
-
Clock Source