Samsung S3C6400X User Manual page 335

VECTORED INTERRUPT CONTROLLER
Vector Address Register, VICADDRESS
Bits Name
[31:0] VectAddr
Software Priority Mask Register, VICSWPRIORITYMASK
Bits Name
[31:16] Reserved
[15:0] SWPriorityMask
Vector Address Regisgers, VICVECTADDR[0-31]
Bits Name
[31:0] VectorAddr 0-31
Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY
Bits Name
[31:4] Reserved
[3:0] VectPriority
Preliminary product information describe products that are in development,
12-12
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Type Function
Contains the address of the currently active ISR, with
RW
reset value 0x00000000.
A read of this register returns the address of the ISR and
sets the current interrupt as being serviced. A read must
only be performed while there is an active interrupt.
A write of any value to this register clears the current
interrupt. A write must only be performed at the end of an
interrupt service routine.
Type Function
Reserved, read as zero, do not modify
-
Controls software masking of the 16 interrupt priority
RW
levels:
0 = interrupt priority level is masked
1 = interrupt priority level is not masked (reset).
Each bit of the register is applied to each of the 16
interrupt priority levels.
Type Function
Contains ISR vector addresses.
RW
Type Function
Reserved, read as zero, do not modify.
-
Selects vectored interrupt priority level. You can select
RW
any of the 16 vectored interrupt priority levels by
programming the register with the hexadecimal value of
the priority level required, from 0-15.
S3C6400X RISC MICROPROCESSOR