Samsung S3C6400X User Manual page 75

SYSTEM CONTROLLER
Clock gating control register
S3C6400 can disable the clock operation of each IP when it does not require running. The following three
registers control clock disable/enable operation.
REGISTER
HCLK_GATE 0x7E00_F030
PCLK_GATE 0x7E00_F034
SCLK_GATE 0x7E00_F038
HCLK_GATE controls HCLK of all IPs. If a field has '1', then HCLK is supplied. Otherwise, HCLK is masked.
When S3C6400x goes to a power down mode, system controller checks the status of some block, IROM, MEM0,
MEM1, and MFC block. Therefore, bit 25, 22, 21, 0 should be '1' to acknowledge a power down request.
HCLK_GATE
RESERVED [31:30] RESERVED
HCLK_UHOST
HCLK_SECUR
HCLK_SDMA1
HCLK_SDMA0
HCLK_IROM
HCLK_DDR1
HCLK_DDR0
HCLK_MEM1
HCLK_MEM0
HCLK_USB
HCLK_HSMMC2
HCLK_HSMMC1
HCLK_HSMMC0
HCLK_MDP
HCLK_DHOST
HCLK_IHOST
HCLK_DMA1
HCLK_DMA0
HCLK_JPEG
HCLK_CAMIF
HCLK_SCALER
HCLK_2D
HCLK_TV
RESERVED
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-30
Specifications and information herein are subject to change without notice.
ADDRESS R/W
R/W
R/W
R/W
BIT
[29] Gating HCLK for UHOST (0: mask, 1: pass)
[28] Gating HCLK for security sub-system (0: mask, 1: pass)
[27] Gating HCLK for SDMA1 (0: mask, 1: pass)
[26] Gating HCLK for SDMA0 (0: mask, 1: pass)
[25] Gating HCLK for IROM (0: mask, 1: pass)
[24] Gating HCLK for DDR1 (0: mask, 1: pass)
[23] Gating HCLK for DDR0 (0: mask, 1: pass)
[22] Gating HCLK for DMC1 (0: mask, 1: pass)
Gating HCLK for DMC0, SROM, OneNAND, NFCON,
[21]
CFCON (0: mask, 1: pass)
[20] Gating HCLK for USB OTG (0: mask, 1: pass)
[19] Gating HCLK for HSMMC2 (0: mask, 1: pass)
[18] Gating HCLK for HSMMC1 (0: mask, 1: pass)
[17] Gating HCLK for HSMMC0 (0: mask, 1: pass)
[16] Gating HCLK for MDP (0: mask, 1: pass)
[15] Gating HCLK for direct HOST interface (0: mask, 1: pass)
[14] Gating HCLK for indirect HOST interface (0: mask, 1: pass)
[13] Gating HCLK for DMA1 (0: mask, 1: pass)
[12] Gating HCLK for DMA0 (0: mask, 1: pass)
[11] Gating HCLK for JPEG (0: mask, 1: pass)
[10] Gating HCLK for camera interface (0: mask, 1: pass)
[9] Gating HCLK for scaler (0: mask, 1: pass)
[8] Gating HCLK for 2D (0: mask, 1: pass)
[7] Gating HCLK for TV encoder (0: mask, 1: pass)
[6] RESERVED
DESCRIPTION
HCLK clock gating control
PCLK clock gating control
Special clock gating control
DESCRIPTION
S3C6400X RISC MICROPROCESSOR
RESET VALUE
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
RESET VALUE
0x3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1