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Samsung S3F80JB Manuals
Manuals and User Guides for Samsung S3F80JB. We have
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Samsung S3F80JB manual available for free PDF download: User Manual
Samsung S3F80JB User Manual (346 pages)
8-BIT CMOS MICROCONTROLLERS
Brand:
Samsung
| Category:
Computer Hardware
| Size: 4.36 MB
Table of Contents
Table of Contents
4
Chapter 1 Product Overview
19
S3C8/S3F8-Series Microcontrollers
19
S3F80JB Microcontroller
19
Features
20
Block Diagram (32-Pin Package)
21
Block Diagram (44-Pin Package)
22
Pin Assignments
23
Pin Assignment Diagram (32-Pin SOP Package)
23
Pin Assignment Diagram (44-Pin QFP Package)
24
Pin Descriptions of 32-SOP
25
Pin Descriptions of 44-QFP
26
Pin Circuits
28
Pin Circuit Type 1 (Port 0 and Port2)
28
Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)
29
Pin Circuit Type 3 (P3.0)
30
Pin Circuit Type 4 (P3.1)
31
Pin Circuit Type 5 (P3.2 and P3.3)
31
Pin Circuit Type 6 (Nreset)
32
Overview
33
Chapter 2 Address Spaces
34
Program Memory
34
Smart Option
35
Register Architecture
37
Internal Register File Organization
38
Register Page Pointer (PP)
39
Register Set1
40
Register Set 2
40
Prime Register Space
41
Set 1, Set 2, and Prime Area Register Map
41
Working Registers
42
Byte Working Register Areas (Slices)
42
Using the Register Pointers
43
Contiguous 16-Byte Working Register Block
43
Setting the Register Pointers
43
Non-Contiguous 16-Byte Working Register Block
44
Using the Rps to Calculate the Sum of a Series of Registers
44
Register Addressing
45
Bit Register Pair
45
Register File Addressing
46
Common Working Register Area (C0H-CFH)
47
4-Bit Working Register Addressing
48
Addressing the Common Working Register Area
48
Bit Working Register Addressing Example
49
8-Bit Working Register Addressing
50
Bit Working Register Addressing Example
51
System and User Stacks
52
Stack Operations
52
Standard Stack Operations Using PUSH and POP
53
Chapter 3 Addressing Modes
54
Overview
54
Register Addressing Mode (R)
55
Working Register Addressing
55
Indirect Register Addressing Mode (IR)
56
Indirect Register Addressing to Register File
56
Indirect Register Addressing to Program Memory
57
Indirect Working Register Addressing to Register File
58
Indirect Working Register Addressing to Program or Data Memory
59
Indexed Addressing Mode (X)
60
Indexed Addressing to Register File
60
Indexed Addressing to Program or Data Memory with Short Offset
61
Indexed Addressing to Program or Data Memory
62
Direct Address Mode (DA)
63
Direct Addressing for Load Instructions
63
Direct Addressing for Call and Jump Instructions
64
Indirect Address Mode (IA)
65
Indirect Addressing
65
Relative Address Mode (RA)
66
Relative Addressing
66
Immediate Mode (IM)
67
Immediate Addressing
67
Chapter 4 Control Registers
68
Overview
68
Mapped Registers (Bank0, Set1)
69
Mapped Registers (Bank1, Set1)
70
Register Description Format
71
BTCON Basic Timer Control Register
72
CACON Counter a Control Register
73
CLKCON System Clock Control Register
74
CMOD Comparator Mode Register
75
CMPSEL Comparator Input Selection Register
76
EMT External Memory Timing Register
77
FLAGS System Flags Register
78
FMCON Flash Memory Control Register
79
FMSECH Flash Memory Sector Address Register (High Byte)
80
FMSECL Flash Memory Sector Address Register (Low Byte)
80
FMUSR Flash Memory User Programming Enable Register
80
IMR Interrupt Mask Register
81
IPH Instruction Pointer (High Byte)
82
IPL Instruction Pointer (Low Byte)
82
IPR Interrupt Priority Register
83
LVD Flag
85
LVDCON LVD Control Register
85
P0CONL Port 0 Control Register (Low Byte)
87
P0INT Port 0 External Interrupt Enable Register
88
P0PND Port 0 External Interrupt Pending Register
89
P0PUR Port 0 Pull-Up Resistor Enable Register
90
P1CONH Port 1 Control Register (High Byte)
91
P1CONL Port 1 Control Register (Low Byte)
92
P2CONH Port 2 Control Register (High Byte)
93
P2CONL Port 2 Control Register (Low Byte)
94
P2INT Port 2 External Interrupt Enable Register
95
P2PND Port 2 External Interrupt Pending Register
96
P3CON Port 3 Control Register
98
Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package
99
P345CON Port3[4:5] Control Register
100
P4CON Port 4 Control Register
101
P4CONH Port 4 Control Register (High Byte)
102
P4CONL Port 4 Control Register (Low Byte)
103
PP Register Page Pointer
104
RP0 Register Pointer 0
105
RP1 Register Pointer 1
105
SPL Stack Pointer (Low Byte)
106
STOPCON Stop Control Register
106
SYM System Mode Register
107
T1CON Timer 1 Control Register
109
T2CON Timer 2 Control Register
110
Chapter 5 Interrupt Structure
111
Overview
111
Interrupt Types
112
S3C8/S3F8-Series Interrupt Types
112
S3F80JB Interrupt Structure
114
Interrupt Vector Addresses
115
ROM Vector Address Area
115
S3F80JB Interrupt Vectors
116
Enable/Disable Interrupt Instructions (EI, DI)
117
System-Level Interrupt Control Registers
117
Interrupt Control Register Overview
117
Interrupt Processing Control Points
118
Interrupt Function Diagram
118
Peripheral Interrupt Control Registers
119
Vectored Interrupt Source Control and Data Registers
119
System Mode Register (SYM)
120
Interrupt Mask Register (IMR)
121
Interrupt Priority Register (IPR)
122
Interrupt Request Priority Groups
122
Interrupt Priority Register (IPR)
123
Interrupt Request Register (IRQ)
124
Interrupt Pending Function Types
125
Interrupt Source Polling Sequence
126
Interrupt Service Routines
126
Generating Interrupt Vector Addresses
127
Nesting of Vectored Interrupts
127
Instruction Pointer (IP)
127
Fast Interrupt Processing
127
Chapter 6 Instruction Set
129
Overview
129
Instruction Group Summary
130
Flags Register (FLAGS)
134
System Flags Register (FLAGS)
134
Flag Descriptions
135
Instruction Set Notation
136
Flag Notation Conventions
136
Instruction Set Symbols
136
Instruction Notation Conventions
137
Opcode Quick Reference
138
Condition Codes
140
Instruction Descriptions
141
ADC Add with Carry
142
ADD Add
143
AND Logical and
144
BAND Bit and
145
BCP Bit Compare
146
BITC Bit Complement
147
BITR Bit Reset
148
BITS Bit Set
149
BTJRF Bit Test, Jump Relative on False
151
BTJRT Bit Test, Jump Relative on True
152
BXOR Bit XOR
153
CALL Call Procedure
154
CCF Complement Carry Flag
155
CLR Clear
156
COM Complement
157
CP Compare
158
CPIJE Compare, Increment, and Jump on Equal
159
CPIJNE Compare, Increment, and Jump on Non-Equal
160
DA Decimal Adjust
161
DA Decimal Adjust
162
DEC Decrement
163
DECW Decrement Word
164
DIV Divide (Unsigned)
166
DJNZ Decrement and Jump if Non-Zero
167
EI Enable Interrupts
168
ENTER Enter
169
EXIT Exit
170
IDLE Idle Operation
171
INC Increment
172
INCW Increment Word
173
IRET Interrupt Return
174
JP Jump
175
JR Jump Relative
176
LD Load
177
LDB Load Bit
179
LDC/LDE Load Memory
180
LDC/LDE Load Memory
181
LDCD/LDED Load Memory and Decrement
182
LDCI/LDEI Load Memory and Increment
183
LDCPI/LDEPI Load Memory with Pre-Increment
185
LDW Load Word
186
MULT Multiply (Unsigned)
187
NEXT Next
188
NOP no Operation
189
OR Logical or
190
POP Pop from Stack
191
POPUD Pop User Stack (Decrementing)
192
POPUI Pop User Stack (Incrementing)
193
PUSH Push to Stack
194
PUSHUD Push User Stack (Decrementing)
195
PUSHUI Push User Stack (Incrementing)
196
RCF Reset Carry Flag
197
RET Return
198
RL Rotate Left
199
RLC Rotate Left through Carry
200
RR Rotate Right
201
RRC Rotate Right through Carry
202
SB0 Select Bank 0
203
SB1 Select Bank 1
204
SBC Subtract with Carry
205
SCF Set Carry Flag
206
SRA Shift Right Arithmetic
207
Srp/Srp0/Srp1
208
Set Register Pointer
208
STOP Stop Operation
209
SUB Subtract
210
SWAP Swap Nibbles
211
TCM Test Complement under Mask
212
TM Test under Mask
213
WFI Wait for Interrupt
214
XOR Logical Exclusive or
215
System Clock Circuit
216
Overview
216
Main Oscillator Circuit (External Crystal or Ceramic Resonator)
216
External Clock Circuit
216
Clock Status During Power-Down Modes
217
System Clock Circuit Diagram
217
System Clock Control Register (CLKCON)
218
Reset Sources
219
Overview
219
RESET Sources of the S3F80JB
220
RESET Block Diagram of the S3F80JB
221
Reset Mechanism
222
External Reset Pin
222
Watch Dog Timer Reset
222
LVD Reset
222
RESET Block Diagram by LVD for the S3F80JB in STOP MODE
222
Internal Power-On Reset
223
Internal Power-On Reset Circuit
223
Timing Diagram for Internal Power-On Reset Circuit
224
External Interrupt Reset
225
Reset Timing Diagram for the S3F80JB in STOP Mode by IPOR
225
Stop Error Detection & Recovery
226
Reset Condition in STOP Mode When IPOR / LVD Control Bit Is "0"
226
Power-Down Modes
227
Idle Mode
227
Back-Up Mode
228
Block Diagram for Back-Up Mode
228
Timing Diagram for Back-Up Mode Input and Released by LVD
228
Stop Mode
229
Sources to Release Stop Mode
230
System Reset Operation
232
Hardware Reset Values
233
Set 1, Bank 0 Register Values after Reset
233
Set 1, Bank 1 Register Values after Reset
235
Reset Generation According to the Condition of Smart Option
236
Recommendation for Unusued Pins
237
Guideline for Unused Pins to Reduced Power Consumption
237
Summary Table of Back-Up Mode, Stop Mode, and Reset Status
238
Summary of each Mode
238
Overview
239
S3F80JB Port Configuration Overview (44-QFP)
240
S3F80JB Port Configuration Overview (32-SOP)
241
Port Data Registers
242
Port Data Register Summary
242
Pull-Up Resistor Enable Registers (Port 0 and Port 2 Only)
243
Basic Timer (BT)
244
Overview
244
Basic Timer Control Register (BTCON)
245
Basic Timer Function Description
246
Timer 0 Control Register (T0CON)
247
Timer 0 DATA Register (T0DATA)
248
Timer 0 Control Register (T0CON)
248
Timer 0 Function Description
249
Simplified Timer 0 Function Diagram: Interval Timer Mode
249
Simplified Timer 0 Function Diagram: PWM Mode
250
Simplified Timer 0 Function Diagram: Capture Mode
251
Basic Timer and Timer 0 Block Diagram
252
Configuring the Basic Timer
253
Programming Timer 0
255
Overview
256
Timer 1 Overflow Interrupt
257
Timer 1 Capture Interrupt
257
Simplified Timer 1 Function Diagram: Capture Mode
257
Timer 1 Match Interrupt
258
Simplified Timer 1 Function Diagram: Interval Timer Mode
258
Timer 1 Block Diagram
259
Timer 1 Control Register (T1CON)
260
Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)
261
Overview
262
Counter a Block Diagram
263
Counter a Control Register (CACON)
264
Counter a Registers
264
Counter a Pulse Width Calculations
265
Counter a Output Flip-Flop Waveforms in Repeat Mode
266
To Generate 38 Khz, 1/3Duty Signal through P3.1
267
To Generate a One Pulse Signal through P3.1
268
Overview
269
Timer 2 Overflow Interrupt
270
Timer 2 Capture Interrupt
270
Simplified Timer 2 Function Diagram: Capture Mode
270
Timer 2 Match Interrupt
271
Simplified Timer 2 Function Diagram: Interval Timer Mode
271
Timer 2 Block Diagram
272
Timer 2 Control Register (T2CON)
273
Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
274
Overview
275
Comparator Block Diagram for the S3F80JB
276
Comparator Operation
277
Conversion Characteristics
277
Comparator Mode Register (CMOD)
278
Comparator Input Selection Register (CMPSEL)
278
Comparator Result Register (CMPREG)
279
Overview
280
Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode
281
Program Memory Address Space
282
Smart Option
283
ISP Reset Vector and ISP Sector Size
284
Flash Memory Control Registers (User Program Mode)
285
Flash Memory User Programming Enable Register (FMUSR)
285
Flash Memory Sector Address Registers
286
Sector Erase
287
Sector Configurations in User Program Mode
287
Sector Erase Flowchart in User Program Mode
288
Sector Erase
289
Programming
291
Byte Program Flowchart in a User Program Mode
292
Program Flowchart in a User Program Mode
293
Programming
294
Reading
296
Hard Lock Protection
297
Low Voltage Detector Control Register (LVDCON)
300
Overview
301
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) ·························
305
Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································
306
Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································
307
Stop Mode Release Timing When Initiated by an External Interrupt·························
308
Stop Mode Release Timing When Initiated by a Reset·············································
308
Stop Mode Release Timing When Initiated by a LVD ···············································
309
Input Timing for Reset (Nreset Pin)·······································································
310
Pin SOP Package Dimension
328
Overview······················································································································································
328
Pin QFP Package Dimension
329
Target Boards
330
Overview······················································································································································
330
Programming Socket Adapter
330
TB80JB Target Board
331
TB80JB Target Board Configuration·········································································
331
Pin Connector Pin Assignment for TB80JB ·························································
334
TB80JB Adapter Cable for 44-QFP Package ···························································
334
OTP/MTP Programmer (Writer)
336
Important Note
342
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