Samsung S3C6400X User Manual page 149

S3C6400X RISC MICROPROCESSOR
INTPOL
IOBE
RDYCONF
Reserved
HF
WM
BWPS
Note: While OneNAND Controller does not obtain memory bus, updating MEM_CFG is stalled, and if another
write access to MEM_CFG, it is possible to be lost. After writing MEM_CFG register, read system configuration
register (0xF221) on OneNAND by using MAP11 command to check that register updated.
BURST LENGTH REGISTER
Register
BURST_LEN0
BURST_LEN1
BURST_LENn
Reserved
BURST_LENGTH
• 1 = High for ready.
[6] INT signal polarity.
• 0 = Low for interrupt pending.
• 1 = High for interrupt pending.
[5] I/O Buffer enable for INT and RDY signals, INT and RDY
outputs are hi-Z at start up, bit 7 and 6 become valid after
IOBE is set to 1. IOBE can be reset only by Cold reset.
• 0 = Disable.
• 1 = Enable.
[4] RDY configuration.
• 0 = Active with valid data.
• 1 = Active one clock before valid data.
[3]
[2] High frequency enable.
• 0 = High frequency disable. (66MHz and under)
• 1 =High frequency enable. (over 66MHz)
[1] Sets the transfer mode for write operations as synchronous or
asynchronous. Default value is 0x0. Set by software during
initialization.
• 0 = Asynchronous Mode.
• 1 = Activate Synchronous Mode.
[0] Boot buffer write protected status
• 0 = Locked.
• 1 = Unlocked.
Address R/W
0x70100010 R/W Bank0 Burst Length Register
0x70180010
Bit
[31:16]
[5:0] Sets the burst length (halfword count) of the controller. This
register has no default value. The value should be the same to
or less than the value of OneNAND 0xF221 burst length field
is recommended. Set by software during initialization.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
ONENAND CONTROLLER
0
0
0
0
0
0
Reset Value
0x0000
Initial State
0
0
7-19