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S3C6400X RISC MICROPROCESSOR
13
SECURITY SUB-SYSTEM
OVERVIEW
Security sub-system (SsS) is a crypto function accelerator targeted for general purpose mobile processors
such as the Application Processor (AP) and Modem chip.
The architecture of SsS also provides high-speed bulk data processing, by providing double-layer AHB bus
and FIFOs. FIFO-Rx and FIFO-Tx can be programmed to monitor AES or DES/3DES or SHA-1/PRNG
module, and automatically transfer input/output data from the target module. This scheme does not require
CPU's intervention and can achieve high-speed bulk data processing.
Figure 13-1 shows the block diagram of the SsS, and its main features are as follows.
FEATURES
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Symmetric key accelerator
AES
DES/3DES
Hash engine
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SHA-1
H/W HMAC support
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Random Number Generator
PRNG 320-bit generation per 160 cycles
FIFO-Rx/Tx : (two 32-word) for input and output streaming.
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DMA I/F to SDMA1(Security DMA 1)
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: ECB, CBC, CTR mode support
: ECB, CBC mode support
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SECURITY SUB-SYSTEM
13-1
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