Samsung S3C6400X User Manual page 845

USB2.0 HS OTG
Register Address
HPTXSTS 0x7C00_0410
HPTXSTS
PTxQTop [31:24]
PTxQSpcAvail [23:16]
PTxFSpcAvail
HOST ALL CHANNELS INTERRUPT REGISTER (HAINT)
When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application
using the Host Channels Interrupt bit of the Core Interrupt register. There is one interrupt bit per channel, up to a
maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the
corresponding Host Channel-n Interrupt register.
Register Address
HAINT 0x7C00_0414
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-38
Specifications and information herein are subject to change without notice.
R/W
R Host Periodic Transmit FIFO/Queue Status Register
Bit R/W
RO Top of the Periodic Transmit Request Queue
This indicates the entry in the Periodic Tx Request
Queue that is currently being processes by the MAC.
This register is used for debugging.
· Bit [31] : Odd/Even (micro)frame
- 1'b0 : send in even (micro)frame
- 1'b1 : send in odd (micro)frame
· Bits [30:27] : Channel/endpoint number
· Bits [26:25] : Type
-2'b00 : IN/OUT
-2'b01 : Zero-length packet
-2'b10 : CSPLIT
-2'b11 : Disable channel command
· Bit[24] : Terminate
RO Periodic Transmit Request Queue Space Available
Indicates the number of free locations available to be
written in the Periodic Transmit Request Queue. This
queue holds both IN and OUT requests.
· 8'h0 : Periodic Transmit Request Queue is full
· 8'h1 : 1 location available
· 8'h2 : 2 location available
· n : n locations available (0≤ n≤ 8)
· Others : Reserved
[15:0] RO Periodic Transmit Data FIFO Space Available
Indicates the number of free locations available to be
written to in the Periodic TxFIFO.
Values are in terms of 32-bit words
· 16'h0: Periodic TxFIFO is full
16'h1: 1 word available
· 16'h2: 2 words available
· n: n words available (0≤ n≤ 8)
· Others: Reserved
R/W
R
Description
Description
Description
Host All Channels Interrupt Register
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
·
Reset Value
32 bits
8'h0
32 bits