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S3C6400X RISC MICROPROCESSOR
BIT Processor operations
Description of BIT Processor Registers
These host interface registers can be partitioned into three categories according to their usage as listed below:
BIT Processor Control Registers:
Host interface registers in this category will be used to update or show BIT processor status to host
processors. Most of these registers will be used for initializing BIT processor during boot-up.
BIT Processor Global Registers:
Host interface registers in this category will be used to store all the global variables which will be kept
even while active instance is changed. Basically all the buffer addresses and some global options will be
safely stored into these registers.
BIT Processor Command I/O Registers:
Host interface registers in this category will be overwritten or updated whenever new command is
transmitted from Host processor. All the commands with input arguments and all the corresponding
responses with return values will be handled using these registers.
Address 0x000 ~ 0x0FC (64 registers address space) are H/W registers. This register has reset values and the
function is fixed (not configurable), and Address 0x100 ~ 0x1FC (64 registers) are general purpose S/W registers.
They have no reset values and are configurable by BIT firmware. They are mainly used for interface between host
and BIT processor.
Upper 32 registers (address 0x100 ~ 0x17C) are used as static parameters. The meanings or functions of those
registers are not changed for all kinds of run commands (SEQ_INIT, SEQ_END, PICTURE_RUN, ...) and applied
to whole commands and processes. Lower 32 registers (address 0x180 ~ 0x1FC) are used as temporal command
arguments. The meanings or functions of those registers may be changed for each run command.
For example BitStreamCtrl register is applied to whole processes. It means all encoding/decoding operations are
affected by BitStreamCtrl register. But CMD_DEC_SEQ_STRIDE register is applied to only current running
process of executing DEC_SEQ_INIT command. So that register (address 0x18C) will be used as different
function for other commands. The value of [LineStride] is applied to only current process so all processes may
have different line stride offset because BIT processor reads the CMD_DEC_SEQ_STRIDE register during
executing DEC_SEQ_INIT command and stores [LineStride] value to internal memory.
BIT Processor Code Download
BIT processor has 6144 words internal code memory (word : 16 bit). The internal code memory is used as the
instruction cache controlled by BIT firmware. The total code image may be bigger than 6144 words and must
reside in SDRAM. BIT firmware loads appropriate code image from SDRAM at run time. Host must inform the
start SDRAM byte address of code image to the BIT processor by set [CodeBufAddr] register.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-98
Specifications and information herein are subject to change without notice.
MULTI-FORMAT VIDEO CODEC
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