Samsung S3C6400X User Manual page 178

S3C6400X RISC MICROPROCESSOR
EnbRnBINT
RnB_TransMode
MainECCLock
SpareECCLock
InitMECC
InitSECC
Reserved
Reg_nCE1
Reg_nCE0
MODE
program or erase locking area (the area setting in
NFSBLK (0x70200020) to NFEBLK (0x70200024)- 1).
[9] RnB status input signal transition interrupt control
0: Disable RnB interrupt 1: Enable RnB interrupt
[8] RnB transition detection configuration
0: Detect rising edge
[7] Lock Main area ECC generation
0: Unlock Main area ECC
Main area ECC status register is
NFMECC0/1(0x70200034/38),
[6] Lock Spare area ECC generation.
0: Unlock Spare ECC
Spare area ECC status register is
NFSECC(0x7020003C),
[5] 1: Initialize main area ECC decoder/encoder (write-only)
[4] 1: Initialize spare area ECC decoder/encoder (write-only)
[3] Reserved (HW_nCE)
[2] NAND Flash Memory nGCS[3] signal control
0: Force nGCS[3] to low(Enable chip select)
1: Force nGCS[3] to High(Disable chip select)
Note: Even Reg_nCE1 and Reg_nCE0 are set to zero
simultaneously, only one of them is asserted.
[1] NAND Flash Memory nGCS[2] signal control
0: Force nGCS[2] to low(Enable chip select)
1: Force nGCS[2] to High(Disable chip select)
Note: During boot time, it is controlled automatically.
This value is only valid while MODE bit is 1
[0] NAND Flash controller operating mode
0: NAND Flash Controller Disable (Don't work)
1: NAND Flash Controller Enable
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
NAND FLASH CONTROLLER
1: Detect falling edge
1: Lock Main area ECC
1: Lock Spare ECC
0
0
1
1
0
0
0
1
1
0
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