Samsung S3C6400X User Manual page 355

SECURITY SUB-SYSTEM
SECURITY SUB-SYSTEM DES/3DES MODULE
TDES_RX_CTRL
Register Address
TDES_Rx_CTRL 0x7D20_0000 R/W TDES control / status register
TDES_Rx_CTRL
WrPrivMismatch
RdPrivMismatch
Reserved [29:8] Reserved
TdesOutReady
TdesInReady
DesOrTdes
TdesMode
TdesOpDirection
TdesIntMode
TdesOpEnable
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
13-18
Specifications and information herein are subject to change without notice.
R/W
Bit
SFR Write Access Privilege Mismatch Status bit. If set to '1',
[31]
SFR Write Access Privilege Mismatch is occurred.
SFR Read Access Privilege Mismatch Status bit. If set to '1',
[30]
SFR Read Access Privilege Mismatch is occurred.
If set to '1', AES Out Buffer is Full, and ARM or Rx FiFo is
[7]
permitted to Read current 128bits result data
If set to '1', TDES Input Buffer is Empty, and ARM or Rx FiFo is
[6]
permitted to write next 128bits data.
DES or TDES Operation Selection Bit
[5]
0 : DES Only Mode
TDES Mode Selection Bit
[4:3]
01 : ECB Mode
TDES Operation Direction Selection Bit.
[2]
0 : Encryption
TDES Operation End Mode Selection Bit
[1]
0 : Polling Mode
If set to '1', TDES starts operation by ARM. If the
[0]
des_or_tdes_op_done is generated, It becomes '0'.
S3C6400X RISC MICROPROCESSOR
Description
Description
1 : TDES Mode
10 : CBC Mode
1 : Decryption
1 : Interrupt Mode
Reset Value
0x0000_0040
Initial State
0b
0b
0x0000_00
0b
1b
0b
00b
0b
0b
0b