Samsung S3C6400X User Manual page 926

HSMMC CONTROLLER
[0]
Note: Host Driver may check if interrupt is actually cleared by polling or monitoring the INTREQ port. If HCLK is
much faster than SDCLK, it takes long time to be cleared for the bits actually.
Note : Card Interrupt status bit keeps previous value until next card interrupt period (level interrupt) and can be
cleared when write to 1 (RW1C).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-50
Specifications and information herein are subject to change without notice.
Relation between Transfer Complete and Data
Transfer Data Timeout
Complete Error
0 0
0 1
1 Don't care
'1' = Data Transfer Complete
This bit is set when get the end bit of the command response. (Except Auto
CMD12) Refer to Command Inhibit (CMD) in the Present State register.
The table below shows that Command Timeout Error has higher priority than
Command Complete. If both bits are set to 1, it can be considered that the
response was not received correctly. (RW1C)
Command Command
Complete Timeout Error
0 0
Don't care 1
1 0
Meaning of the status
Interrupted by another factor
Timeout occur during transfer
Data transfer complete
'0' = No transfer complete
Command Complete
Meaning of the status
Interrupted by another factor
Response not received within
64 SDCLK cycles.
Response received
'1' = Command Complete
'0' = No command complete
S3C6400X RISC MICROPROCESSOR
0