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S3C6400X RISC MICROPROCESSOR
HCINT4
0x588
HCINTMSK4
0x58C
HCTSIZ4
0x580
HCDMA4
0x584
HCCHAR5
0x5A0
HCSPLT5
0x5A4
HCINT5
0x5A8
HCINTMSK5
0x5AC
HCTSIZ5
0x5B0
HCDMA5
0x5B4
HCCHAR6
0x5C0
HCSPLT6
0x5C4
HCINT6
0x5C8
HCINTMSK6
0x5CC
HCTSIZ6
0x5D0
HCDMA6
0x5D4
HCCHAR7
0x5E0
HCSPLT7
0x5E4
HCINT7
0x5E8
HCINTMSK7
0x5EC
HCTSIZ7
0x5F0
HCDMA7
0x5F4
HCCHAR8
0x600
HCSPLT8
0x604
HCINT8
0x608
HCINTMSK8
0x60C
HCTSIZ8
0x610
HCDMA8
0x614
HCCHAR9
0x620
HCSPLT9
0x624
HCINT9
0x628
HCINTMSK9
0x62C
HCTSIZ9
0x630
HCDMA9
0x634
HCCHAR10
0x640
HCSPLT10
0x644
HCINT10
0x648
HCINTMSK10
0x64C
R/W
Host Channel 4 Interrupt Register
R/W
Host Channel 4 Interrupt Mask Register
R/W
Host Channel 4 Transfer Size Register
R/W
Host Channel 4 DMA Address Register
R/W
Host Channel 5 Characteristics Register
R/W
Host Channel 5 Spilt Control Register
R/W
Host Channel 5 Interrupt Register
R/W
Host Channel 5 Interrupt Mask Register
R/W
Host Channel 5 Transfer Size Register
R/W
Host Channel 5 DMA Address Register
R/W
Host Channel 6 Characteristics Register
R/W
Host Channel 6 Spilt Control Register
R/W
Host Channel 6 Interrupt Register
R/W
Host Channel 6 Interrupt Mask Register
R/W
Host Channel 6 Transfer Size Register
R/W
Host Channel 6 DMA Address Register
R/W
Host Channel 7 Characteristics Register
R/W
Host Channel 7 Spilt Control Register
R/W
Host Channel 7 Interrupt Register
R/W
Host Channel 7 Interrupt Mask Register
R/W
Host Channel 7 Transfer Size Register
R/W
Host Channel 7 DMA Address Register
R/W
Host Channel 8 Characteristics Register
R/W
Host Channel 8 Spilt Control Register
R/W
Host Channel 8 Interrupt Register
R/W
Host Channel 8 Interrupt Mask Register
R/W
Host Channel 8 Transfer Size Register
R/W
Host Channel 8 DMA Address Register
R/W
Host Channel 9 Characteristics Register
R/W
Host Channel 9 Spilt Control Register
R/W
Host Channel 9 Interrupt Register
R/W
Host Channel 9 Interrupt Mask Register
R/W
Host Channel 9 Transfer Size Register
R/W
Host Channel 9 DMA Address Register
R/W
Host Channel 10 Characteristics Register
R/W
Host Channel 10 Spilt Control Register
R/W
Host Channel 10 Interrupt Register
R/W
Host Channel 10 Interrupt Mask Register
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
USB2.0 HS OTG
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
26-9
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