Samsung S3C6400X User Manual page 59

SYSTEM CONTROLLER
5. SYSCON changes clock source from external oscillator to PLL output if PLL is used.
6. SYSCON releases self-refresh mode requests to memory controllers.
7. The memory controllers send acknowledges when they are ready.
8. SYSCON releases AXI/AHB bus down request.
9. SYSCON releases reset signal of ARM1176 (only applied for DEEP-STOP mode)
DEEP-STOP mode
Most mobile applications require longer standby period and reasonable response time from low power state.
DEEP-STOP mode is focused for these specific requirements. External power ON/OFF control generally requires
long transition time (~3ms). When the boot device is NAND, the boot code is already loaded into the stepping-
stone, and retained during DEEP-STOP mode. Thus, the boot code-copying period can be ignored.
Figure 3-16 shows the status at DEEP-STOP mode. The black boxes denote power-gating blocks and eliminate
leakage current during DEEP-STOP mode while top module retains the previous states as STOP mode.
Figure 3-16. Power domains at DEEP-STOP mode (ARM11 is OFF and lost internal state)
Since the entering and exiting sequence is similar to STOP mode, refer to STOP mode sequence for entering and
exiting sequence of DEEP-STOP mode.
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SLEEP mode
In SLEEP mode, all hardware logics excepting ALIVE and RTC blocks, are power-OFF using external power-
regulator. SLEEP mode supports the longest standby period, while user software must store all internal status to
external storage devices. ALIVE block waits an external wake-up event and RTC stores time information. User
software can configure wake-up source and the status of I/O pins with GPIO configuration.
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All sub-blocks must be power-ON before S3C6400 enters SLEEP mode. Otherwise, it creates unexpected problem during
wakeup sequence.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
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Specifications and information herein are subject to change without notice.
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AXI (64b)
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ARM11
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AXI (32b)
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S3C6400X RISC MICROPROCESSOR
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