Samsung S3C6400X User Manual page 58

S3C6400X RISC MICROPROCESSOR
STOP mode
In STOP mode, sub-power domains, which are highlighted in black boxes, are OFF with internal power-gating
circuitry as shown in Figure 3-15. Other blocks which are highlighted in white boxes and ARM1176, are retaining
the previous state (clock-gating state). Thus, when external wake-up events occur, internal states are recovered
without software assistance. STOP mode gives fast response time, but requires a little leakage current. (Please
refer to the electrical specification for the detailed information.)
Figure 3-15. Power domains at STOP mode (Domains highlighted in white represent clock-off domain and
domains highlighted in black represent power-gating domain)
The following are the STOP mode entering sequence:
1. User software sets PWR_CFG[6:5] as STOP mode
2. User software generates STANDBYWFI signal by MCR instruction (MCR p15, 0, Rd, c7, c0, 4)
3. SYSCON requests bus controller to finish current AHB bus transaction.
4. AHB bus controller sends acknowledge to SYSCON after current bus transaction is completed.
5. SYSCON requests DOMAIN-V to finish current AXI-bus transaction.
6. AXI bus controller sends acknowledge to SYSCON after current bus transaction is completed.
7. SYSCON requests external memory controllers to enter into self-refresh mode, since the contents in the
external memory must be preserved during STOP mode.
8. The memory controllers send acknowledges when they are self-refresh mode.
9. SYSCON changes clock source from PLL output to external oscillator if PLL is used.
10. SYSCON disables power-gating circuitries to eliminate leakage current. (only applied for DEEP-STOP mode)
11. SYSCON disables PLL operations and crystal oscillator.
To exit from STOP mode, all wake-up sources excepting normal interrupts are available. The following are the
wake-up sequence from STOP mode:
1. SYSCON asserts reset signal of ARM1176 during transition period to NORMAL mode (only applied for DEEP-
STOP mode)
2. SYSCON enables crystal oscillator and wait for oscillator stable period, which is configured by OSC_STABLE.
3. SYSCON enables clock-gating circuitries to supply operating power and wait for stable time, which is
configured by MTC_STABLE. (only applied for DEEP-STOP mode)
4. SYSCON enables PLL logics and wait for PLL locking period, which is configured by A/M/EPLL_LOCK.
DOMAIN DOMAIN
V I
DOMAIN
X
ARM11
PERIPHERAL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DOMAIN DOMAIN
MEMSYS
P F
AXI (64b)
DOMAIN DOMAIN DOMAIN
T M
AXI (32b)
APB (32b)
SYSTEM CONTROLLER
S
3-13