Samsung S3C6400X User Manual page 314

DMA
Raw error interrupt status register, DMACRawIntErrorStatus
The DMACRawIntErrorStatus register is read-only. It indicates which DMA channels are requesting an error
interrupt prior to masking. A HIGH bit indicates that the error interrupt request is active prior to masking.
Table 11-8 shows the bit assignment of register of the DMACRawIntErrorStatus register.
DMACRawIntErrorStatus
RawIntErrorStatus
Enable channel register, DMACEnbldChns
The DMACEnbldChns register is read-only and indicates which DMA channels are enabled, as indicated by the
Enable bit in the DMACCxConfiguration register. A HIGH bit indicates that a DMA channel is enabled. A bit is
cleared on completion of the DMA transfer.
Table 11-9 shows the bit assignment of the DMACEnbldChns register.
DMACEnbldChns
EnabledChannels
Software burst request register, DMACSoftBReq
The DMACSoftBReq register is read/write and it allows DMA burst requests to be generated by software. A DMA
request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared
when the transaction is complete. Writing 0 to this register has no effect.
Reading the register indicates which sources are requesting DMA burst transfers. A request can be generated from
either a peripheral or the software request register.
Table 11-10 shows the bit assignment of the DMACSoftBReq register.
DMACSoftBReq
SoftBReq
Note: It is recommended that software and hardware peripheral requests are not used at the same time.
Preliminary product information describe products that are in development,
11-18
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 11-8. Bit Assignment of DMACRawIntErrorStatus register
Bits Type
[7:0] R
Table 11-9. Bit Assignment of DMACEnbldChns register
Bits Type
[7:0] R
Table 11-10. Bit Assignment of DMACSoftBReq register
Bits Type
[15:0] R/W
Function
Status of the error interrupt prior to masking
Function
Channel enable status
Function
Software burst request
S3C6400 RISC MICROPROCESSOR