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HSMMC CONTROLLER
BLOCK DIAGRAM
INTREQ
System
Bus
(AHB)
AHB slave I/F
AHB master
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-2
Specifications and information herein are subject to change without notice.
HCLK
Domain
SFR
Status
CMD
ARG
Control
DMA
controller
Figure 27-1. HSMMC block diagram
BaseCLK
Clock Control
Line
Control
FIFO
Control
DPSRAM
S3C6400X RISC MICROPROCESSOR
SDCLK
Domain
Status
RSP
CMDRSP
packet
Control
Control
Status
DATA
packet
Pad
I/F
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