Samsung S3C2416 Manuals

Manuals and User Guides for Samsung S3C2416. We have 1 Samsung S3C2416 manual available for free PDF download: User Manual

Samsung S3C2416 User Manual (672 pages)

16/32-Bit RISC

Brand: Samsung | Category: Computer Hardware | Size: 3.63 MB

Important Notice
2
Revision History
3
Table of Contents
5
Chapter 1 Product Overview

29
- Introduction
  29
- Features
  30
- Block Diagram
  33
- Pin Assignments
  34
  - Signal Descriptions
    51
  - S3C2416 Operation Mode Description
    57
- Memory Map
  58
- Base Address of Special Registers
  59
Chapter 2 System Controller

79
Chapter 3 Bus Matrix & EBI

119
- Overview
  119
- Special Function Registers
  120
Chapter 4 Bus Priorities

123
- Overview
  123
  - Bus Priority MAP
    123
  - Overview
    125
  - Feature
    126
  - Block Diagram
    127
    
    Asynchronous Read
    128
Chapter 5 Static Memory Controller (SMC)

125
- Read Timing Diagram (Drncs = 1, Drnowe = 1)
  129
  - Asynchronous Burst Read
    130
  - Synchronous Read/Synchronous Burst Read
    131
  - Asynchronous Write
    132
- Write Timing Diagram (Drncs = 1, Drnowe = 0)
  133
  - Synchronous Write/ Synchronous Burst Write
    134
  - Bus Turnaround
    135
- Memory Interface with 8-Bit SRAM (2MB)
  137
  - Special Registers
    138
    
    Bank Idle Cycle Control Registers 0-5
    138
    
    Bank Read Wait State Control Registers 0-5
    138
    
    Bank Write Wait State Control Registers 0-5
    139
    
    Bank Output Enable Assertion Delay Control Registers 0-5
    139
    
    Bank Write Enable Assertion Delay Control Registers 0-5
    140
    
    Bank Control Registers 0-5
    141
    
    Bank Onenand Type Selection Register
    143
    
    SMC Status Register
    143
    
    SMC Control Register
    144
  - Overview
    145
  - Block Diagram
    146
  - Mobile DRAM Initialization Sequence
    147
    
    Mobile DRAM(SDRAM or Mobile DDR) Initialization Sequence
    147
    
    DDR2 Initialization Sequence
    147
Chapter 6 Mobile DRAM Controller

145
Chapter 7 NAND Flash Controller

159
- Overview
  159
- Features
  159
- Block Diagram
  160
- Boot Loader Function
  160
- GPC5/6/7 Pin Configuration Table in IROM Boot Mode
  161
- NAND Flash Memory Timing
  161
- NAND Flash Access
  162
- Data Register Configuration
  163
- Steppingstone (8KB in 64KB SRAM)
  163
- 1Bit / 4Bit / 8Bit ECC (Error Correction Code)
  163
- Memory Mapping(NAND Boot and Other Boot)
  168
- NAND Flash Memory Configuration
  169
- NAND Flash Controller Special Registers
  170
  - NAND Flash Controller Register Map
    170
  - Nand Flash Configuration Register
    171
  - Control Register
    173
  - Command Register
    175
  - Address Register
    175
  - Data Register
    175
  - Main Data Area ECC Register
    176
  - Spare Area ECC Register
    176
  - Progrmmable Block Address Register
    177
- Softlock and Lock-Tight
  178
  - NFCON Status Register
    179
  - ECC0/1 Error Status Register
    180
  - Main Data Area ECC0 Status Register
    182
  - Spare Area ECC Status Register
    183
  - 4-Bit ECC Error Patten Register
    183
  - ECC 0/1/2 for 8Bit ECC Status Register
    184
  - 8Bit ECC Main Data ECC 0/1/2/3 Status Register
    185
  - 8Bit ECC Error Pattern Register
    186
  - Overview
    187
  - DMA Request Sources
    188
  - DMA Operation
    189
    
    External DMA Dreq/Dack Protocol
    190
Chapter 8 DMA Controller

187
- Demand/Handshake Mode Comparison
  191
- Burst 4 Transfer Size
  192
  - Examples of Possible Cases
    193
  - DMA Special Registers
    194
    
    DMA Initial Source Register (DISRC)
    194
    
    DMA Initial Source Control Register (DISRCC)
    195
    
    DMA Initial Destination Register (DIDST)
    196
    
    DMA Initial Destination Control Register (DIDSTC)
    197
    
    DMA Control Register (DCON)
    198
    
    DMA Status Register (DSTAT)
    200
    
    DMA Current Source Register (DCSRC)
    201
    
    Current Destination Register (DCDST)
    201
    
    DMA Mask Trigger Register (DMASKTRIG)
    202
    
    DMA Requeset Selection Register (DMAREQSEL)
    203
  - Overview
    205
Chapter 9 Interrupt Controller

205
- Interrupt Group Multiplexing Diagram
  206
  - Interrupt Controller Operation
    207
  - Interrupt Sources
    208
  - Interrupt Priority Generating Block
    210
  - Interrupt Priority
    211
  - Interrupt Controller Special Registers
    212
    
    Source Pending (SRCPND) Register
    214
    
    Interrupt Mode (INTMOD) Register
    216
    
    Interrupt Mask (INTMSK) Register
    218
    
    Interrupt Pending (INTPND) Register
    220
    
    Interrupt Offset (INTOFFSET) Register
    222
    
    Sub Source Pending (SUBSRCPND) Register
    224
    
    Interrupt Sub Mask (INTSUBMSK) Register
    226
    
    Priority Mode Register (Priority_Mode)
    228
    
    Priority Update Register (Priority_Update)
    233
Chapter 10 I/O Ports

235
Chapter 11 Watchdog Timer

279
- Overview
  279
  - Features
    279
- Watchdog Timer Operation
  280
  - Block Diagram
    280
  - Wtdat & Wtcnt
    280
  - Consideration of Debugging Environment
    281
- Watchdog Timer Special Registers
  282
Chapter 12 PWM Timer

285
- Overview
  285
  - Feature
    285
- Bit PWM Timer Block Diagram
  286
  - PWM Timer Operation
    287
    
    Prescaler & Divider
    287
    
    Basic Timer Operation
    288
    
    Auto Reload & Double Buffering
    289
    
    Timer Initialization Using Manual Update Bit and Inverter Bit
    290
    
    Timer Operation
    291
    
    Pulse Width Modulation (PWM)
    292
    
    Output Level Control
    293
    
    DEAD Zone Generator
    294
    
    DMA Request Mode
    295
  - PWM Timer Control Registers
    296
    
    Timer Configuration Register0 (TCFG0)
    296
    
    Timer Configuration Register1 (TCFG1)
    297
    
    Timer Control (TCON) Register
    298
    
    Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)
    300
    
    Timer 0 Count Observation Register (TCNTO0)
    300
    
    Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)
    301
    
    Timer 1 Count Observation Register (TCNTO1)
    301
    
    Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)
    302
    
    Timer 2 Count Observation Register (TCNTO2)
    302
    
    Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)
    303
    
    Timer 3 Count Observation Register (TCNTO3)
    303
    
    Timer 4 Count Buffer Register (TCNTB4)
    304
    
    Timer 4 Count Observation Register (TCNTO4)
    304
Chapter 13 Real Time Clock (RTC)

305
- Overview
  305
  - Features
    305
  - Real Time Clock Operation Description
    306
- RTC Tick Interrupt Clock Scheme
  309
  - External Interface
    310
  - Register Description
    311
  - Individual Register Descriptions
    312
Chapter 14 UART

321
- Overview
  321
  - Features
    321
- Block Diagram
  322
  - UART Operation
    323
- UART AFC Interface
  324
- Interrupts in Connection with FIFO
  326
- Example Showing UART Receiving 5 Characters with 2 Errors
  327
- Irda Function Block Diagram
  328
- Serial I/O Frame Timing Diagram (Normal UART)
  329
- Clock, EPLL Speed Guide
  331
  - UART Special Registers
    332
    
    UART Line Control Register
    332
    
    UART Control Register
    333
    
    UART FIFO Control Register
    335
    
    UART Modem Control Register
    336
    
    UART Tx/Rx Status Register
    337
    
    UART Error Status Register
    338
    
    UART FIFO Status Register
    339
    
    UART Modem Status Register
    340
    
    UART Transmit Buffer Register (Holding Register & FIFO Register)
    341
    
    UART Receive Buffer Register (Holding Register & FIFO Register)
    341
    
    UART Baud RATE Divisor Register
    342
    
    UART Dividing Slot Register
    343
Chapter 15 USB Host Controller

345
- Overview
  345
- USB Host Controller Block Diagram
  345
  - USB Host Controller Special Registers
    346
Chapter 16 USB 2.0 Function

347
- Overview
  347
  - Feature
    347
- Block Diagram
  348
- To Activate USB Port1 for USB 2.0 Function
  349
- SIE (Serial Interface Engine)
  350
- UPH (Universal Protocol Handler)
  350
- UTMI (USB 2.0 Transceiver Macrocell Interface)
  350
- USB 2.0 Function Controller Special Registers
  351
- Indexed Registers
  352
  - Registers
    353
    
    Index Register (IR)
    353
    
    Endpoint Interrupt Register (EIR)
    354
    
    Endpoint Interrupt Enable Register (EIER)
    355
    
    Function Address Register (FAR)
    356
    
    Endpoint Direction Register (EDR)
    357
    
    Test Register (TR)
    358
    
    System Status Register (SSR)
    359
    
    System Control Register (SCR)
    361
    
    EP0 Status Register (EP0SR)
    362
    
    EP0 Control Register (EP0CR)
    363
    
    Endpoint# Buffer Register (EP#BR)
    364
    
    Endpoint Status Register (ESR)
    365
    
    Endpoint Control Register (ECR)
    367
    
    Byte Read Count Register (BRCR)
    368
    
    Byte Write Count Register (BWCR)
    369
    
    MAX Packet Register (MPR)
    370
    
    DMA Control Register (DCR)
    371
    
    DMA Transfer Counter Register (DTCR)
    372
    
    DMA FIFO Counter Register (DFCR)
    373
    
    DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)
    374
    
    DMA Interface Control Register (DICR)
    375
    
    Memory Base Address Register (MBAR)
    376
    
    Memory Current Address Register (MCAR)
    377
    
    Burst FIFO Control Register(FCON)
    377
    
    Burst FIFO Status Register(FSTAT)
    377
    
    AHB Master(DMA) Operation Flow Chart
    378
- IN Transfer Operation Flow
  379
Chapter 17 IIC-Bus Interface

381
- Overview
  381
- IIC-Bus Interface
  381
- IIC-Bus Block Diagram
  382
  - Start and Stop Conditions
    383
  - IIC-Bus Interface
    383
  - Data Transfer Format
    384
  - ACK Signal Transmission
    385
  - Read-Write Operation
    386
  - Bus Arbitration Procedures
    386
  - Abort Conditions
    386
  - Configuring IIC-Bus
    386
  - Flowcharts of Operations in each Mode
    387
- Operations for Master/Receiver Mode
  388
- Operations for Slave/Transmitter Mode
  389
- Operations for Slave/Receiver Mode
  390
  - IIC-Bus Interface Special Registers
    391
    
    Multi-Master IIC-Bus Control (IICCON) Register
    391
    
    Multi-Master IIC-Bus Control/Status (IICSTAT) Register
    392
    
    Multi-Master IIC-Bus Address (IICADD) Register
    393
    
    Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register
    393
    
    Multi-Master IIC-Bus Line Control(IICLC) Register
    394
Chapter 18 1 Introduction

395
- Features
  395
- Color Format Conversion
  396
- Command FIFO
  397
- Rendering Pipeline
  398
  - Primitive Drawing
    398
- Transparent Mode
  400
- Color Expansion
  402
  - Rotation
    403
- Rotation Example
  404
  - Clipping
    405
  - Stencil Test
    405
  - Raster Operation
    405
  - Alpha Blending
    407
  - Register Descriptions
    408
    
    General Registers
    410
    
    Command Registers
    413
    
    Parameter Setting Registers
    415
Chapter 19 HS_SPI Controller

433
- Overview
  433
- Features
  433
- Signal Descriptions
  434
- Operation
  434
  - Operation Mode
    435
  - FIFO Access
    435
  - Trailing Bytes in the Rx FIFO
    435
  - Packet Number Control
    435
  - NCS Control
    435
  - HS_SPI Transfer Format
    436
- Special Function Register Descriptions
  437
  - Setting Sequence of Special Function Register
    437
  - Special Function Register
    438
Chapter 20 SD/MMC Host Controller

447
- Overview
  447
- Features
  447
- Block Diagram
  448
- Sequence
  449
  - SD Card Detection Sequence
    449
  - SD Clock Supply Sequence
    450
  - SD Clock Stop Sequence
    451
  - SD Clock Frequency Change Sequence
    451
  - SD Bus Power Control Sequence
    452
  - Change Bus Width Sequence
    453
  - Timeout Setting for DAT Line
    454
  - SD Transaction Generation
    454
  - SD Command Issue Sequence
    455
  - Command Complete Sequence
    456
  - Command Complete Sequence
    457
  - Transaction Control with Data Transfer Using DAT Line
    458
- Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA)
  461
  - Abort Transaction
    462
  - SDI Special Registers
    463
    
    Configuration Register Types
    463
    
    SDMA System Address Register
    464
    
    Block Size Register
    465
    
    Block Count Register
    467
    
    Argument Register
    468
    
    Transfer Mode Register
    469
- Determination of Transfer Type
  470
  - Command Register
    471
- Relation between Parameters and the Name of Response Type
  472
  - Response Register
    473
  - Buffer Data Port Register
    475
  - Present State Register
    476
- Card Detect State
  480
- Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with Data Transfer
  481
  - Host Control Register
    482
  - Power Control Register
    483
  - Block Gap Control Register
    484
  - Wakeup Control Register
    486
  - Clock Control Register
    487
  - Timeout Control Register
    489
  - Software Reset Register
    490
  - Normal Interrupt Status Register
    492
  - Error Interrupt Status Register
    496
- The Relation between Command CRC Error and Command Timeout Error
  498
- The Relation between Command CRC Error and Command Timeout Error
  506
  - Capabilities Register
    507
  - Maximum Current Capabilities Register
    509
  - Control Register 2
    510
  - Control Register 3
    514
  - Debug Register
    514
  - Control Register 4
    514
  - Force Event Register for Auto CMD12 Error Status
    515
  - Force Event Register for Error Interrupt Status
    516
  - ADMA Error Status Register
    517
  - ADMA System Address Register
    519
  - HOST Controller Version Register
    520
  - Overview
    521
Chapter 21 LCD Controller

522
- Features
  522
- Functional Description
  523
  - Brief of the Sub-Block
    523
  - Data Flow
    523
  - Interface
    524
  - Overview of the Color Data
    525
- BPP(1+5:5:5, BSWP/HWSWP=0) Display Types
  532
- BPP(5:6:5, BSWP/HWSWP=0) Display Types
  533
  - VD Signal Connection
    538
  - Palette Usage
    540
- BPP (A:6:6:6) Palette Data Format
  541
  - Window Blending
    542
    
    Overview
    542
    
    Blending Diagram/Details
    543
- Color Key Block Diagram
  544
- Color Key Function Configurations
  545
  - Vtime Controller Operation
    546
    
    RGB Interface
    546
    
    I80-System Interface
    546
  - Virtual Display
    547
  - RGB Interface I/O
    548
  - LCD CPU Interface I/O (I80-System I/F)
    549
- LCD Signal Muxing Table (RGB and I-80 I/F)
  550
  - Programmer's Model
    551
    
    Overview
    551
  - Overview
    573
    
    Features
    573
  - ADC & Touch Screen Interface Operation
    574
    
    Block Diagram
    574
    
    Function Descriptions
    575
Chapter 22 ADC & Touch Screen Interface

573
- Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode
  576
  - ADC and Touch Screen Interface Special Registers
    577
    
    ADC Control (ADCCON) Register
    577
    
    ADC Touch Screen Control (ADCTSC) Register
    578
    
    ADC Start Delay (ADCDLY) Register
    579
    
    ADC Conversion Data (ADCDAT0) Register
    580
    
    ADC Conversion Data (ADCDAT1) Register
    581
    
    ADC Touch Screen Up-Down Int Check Register (ADCUPDN)
    581
    
    ADC Channel Mux Register (ADCMUX)
    582
  - Overview
    583
  - Signals
    583
  - Block Diagram
    584
  - Functional Descriptions
    584
    
    Master/Slave Mode
    585
    
    DMA Transfer
    586
  - Audio Serial Data Format
    587
    
    IIS-Bus Format
    587
    
    MSB (Left) Justified
    587
    
    LSB (Right) Justified
    587
Chapter 23 IIS Multi Audio Interface

583
- IIS Audio Serial Data Formats
  588
  - Sampling Frequency and Master Clock
    589
  - IIS Clock Mapping Table
    589
  - Programming Guide
    590
    
    Initialization
    590
    
    Play Mode (TX Mode) with DMA
    590
    
    Recording Mode (RX Mode) with DMA
    590
    
    Example Code
    591
- TX FIF0 Structure for BLC = 10 (24-Bits/Channel)
  593
- RX FIF0 Structure for BLC = 10 (24-Bits/Channel)
  596
  - IIS-BUS Interface Special Registers
    597
    
    IIS Control Register (IISCON)
    598
    
    IIS Mode Register (IISMOD)
    600
    
    IIS FIFO Control Register (IISFIC)
    602
    
    IIS Prescaler Control Register (IISPSR)
    602
    
    IIS Transmit Register (IISTXD)
    603
    
    IIS Receive Register (IISRXD)
    603
Chapter 24 AC97 Controller

605
- Overview
  605
  - Feature
    605
  - Signals
    605
- AC97 Controller Operation
  606
  - Block Diagram
    606
  - Internal Data Path
    607
- Operation Flow Chart
  608
- AC-Link Digital Interface Protocol
  609
  - AC-Link Output Frame (SDATA_OUT)
    610
  - AC-Link Input Frame (SDATA_IN)
    611
  - AC-Link Input Frame
    612
- AC97 Power-Down
  613
- Codec Reset
  614
- AC97 Controller State Diagram
  615
- AC97 Controller Special Registers
  616
Chapter 25 PCM Audio Interface

621
- Overview
  621
  - Feature
    621
  - Signals
    621
- PCM Audio Interface
  621
- PCM Timing
  623
  - PCM Input Clock Diagram
    624
  - PCM Registers
    625
  - PCM Register Summary
    625
  - PCM Control Register
    626
  - PCM CLK Control Register
    628
  - The PCM Tx FIFO Register
    629
  - PCM Rx FIFO Register
    630
  - PCM Interrupt Control Register
    631
  - PCM Interrupt Status Register
    634
  - PCM FIFO Status Register
    636
  - PCM Interrupt Clear Register
    637
Chapter 26 Electrical Data

639
Chapter 27 Mechanical Data

671
- Package Dimensions
  671

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Samsung S3C2416 Manuals

Samsung S3C2416 User Manual (672 pages)

Table of Contents

Chapter 1 Product Overview

Chapter 2 System Controller

Chapter 3 Bus Matrix & EBI

Chapter 4 Bus Priorities

Chapter 5 Static Memory Controller (SMC)

Chapter 6 Mobile DRAM Controller

Chapter 7 NAND Flash Controller

Chapter 8 DMA Controller

Chapter 9 Interrupt Controller

Chapter 10 I/O Ports

Chapter 11 Watchdog Timer

Chapter 12 PWM Timer

Chapter 13 Real Time Clock (RTC)

Chapter 14 UART

Chapter 15 USB Host Controller

Chapter 16 USB 2.0 Function

Chapter 17 IIC-Bus Interface

Chapter 18 1 Introduction

Chapter 19 HS_SPI Controller

Chapter 20 SD/MMC Host Controller

Chapter 21 LCD Controller

Chapter 22 ADC & Touch Screen Interface

Chapter 23 IIS Multi Audio Interface

Chapter 24 AC97 Controller

Chapter 25 PCM Audio Interface

Chapter 26 Electrical Data

Chapter 27 Mechanical Data

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