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S3C6400X RISC MICROPROCESSOR
1
0
Table 20-3. Video timing reference codes of ITU-656 8bit format
Note: F = 0 (during field 1), 1 (during field 2)
V = 0 (elsewhere), 1 (during field blanking)
H = 0 (in SAV : Start of Active Video), 1 (in EAV : End of Active Video)
P0, P1, P2, P3 = protection bit
Camera interface logic can catch the video sync bits like H (SAV, EAV) and V (Frame Sync) after
reserved data as "FF-00-00".
C
aution! All external camera interface IOs must not be combined with any other GPIO or bi-directional
ports.
C
aution! All external camera interface IOs are recommended to be shmitt-trigger type IO for noise
reduction.
t1
V S Y N C
t2
H R E F
1
1
t3
Figure 20-4. Sync signal timing diagram
Minimum
t1
12 cycles of Pixel clock
t2
12 cycles of Pixel clock
t3
2 cycles of Pixel clock
t4
12 cycles of Pixel clock
Table 20-4. Sync signal timing requirement
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
0
0
0
0
Maximum
-
-
-
-
CAMERA INTERFACE
P1
P0
t1
t4
20-5
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