Samsung S3C6400X User Manual page 304

DMA
Figure 11-4. Memory-to-memory transaction under DMA flow control
Peripheral-to-peripheral transaction under DMA controller flow control
When the transaction is not a multiple of the burst size, use the following signals:
The single and burst request signals (DMACBREQ and DMACSREQ )of the source peripheral
The burst request signal (DMACBREQ ) of the destination peripheral.
This is shown in Figure 11-4.
Source
peripheral
Figure 11-5. Peripheral-to-peripheral transaction comprising bursts and single requests
The source peripheral follows the same procedure as described in Peripheral-to-memory transaction under DMA
controller flow control. The destination peripheral follows the same procedure as described in Memory-to-peripheral
transaction under peripheral flow control. The next LLI is loaded when all read and write transfers are complete. You
can use the DMACTC signal to indicate the last data has been transferred to the peripherals.
Transfer Direction
Peripheral-to-Memory
Memory-to-Peripheral
Memory-to-Memory
Peripheral-to-Peripheral
Preliminary product information describe products that are in development,
11-8
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Memory
DMACBREQ
DMACSREQ
DMACCLR
AMBA bus
Request Generator
Peripheral
Peripheral
DMA Controller
Peripheral
AMBA bus
DMACBREQ
DMA
controller
DMACCLR
DMACBREQ
DMACBREQ
None
Src : DMACBREQ,
Des : DMACBREQ
S3C6400 RISC MICROPROCESSOR
DMA
controller
Destination
peripheral
Request Signals Used