Samsung S3C6400X User Manual page 87

SYSTEM CONTROLLER
QOS_OVERRIDE0 /
QOS_OVERRID1
RESERVED
QOS_OV_ID
MEM_CFG_STAT
RESERVED
CFG_PRI_TYPE
CFG_FIX_PRI_TYPE
RESERVED
CFG_INDEP_CF
CFG_MUX_FLASH
CFG_NOR_BOOT
CFG_NFCON_BOOT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-42
Specifications and information herein are subject to change without notice.
BIT
[31:16] RESERVED
Override Quality of Service for DMC0/DMC1.
When one or more bits are high, and when the arid match
bits in DMC0/DMC1 are equivalent to the QOS_OV_ID
bits, then the quality of service of the read access is forced
to minimum latency.
AXI master IDs are as follows:
Assigned Master name
AXI ID
0x00 I_BLOCK
0x01 F_BLOCK
[15:0]
0x02 P_BLOCK
0x03 V_BLOCK
0x04 X_BLOCK
0x05 T_BLOCK
0x06 M_BLOCK
0x07 S_BLOCK
0x08 ARMI
0x09 ARMRW
0x0A ARMD
0x0B CF
BIT
[31:16] RESERVED
Current EBI priority scheme. See the EBI_PRI field of
[15]
MEM_SYS_CFG register
Current EBI fixed priority setting. See the EBI_FIX_PRI
[14:12]
field of MEM_SYS_CFG register.
[11] RESERVED
[10] Show CF interface independently.
Show NAND Flash type setting.
0 = Use OneNAND Controller.
[9]
1 = Use NAND Flash Controller.
0 = 16-bit width NOR booting is not selected.
[8]
1 = 16-bit width NOR booting is selected.
[7] 0 = NAND flash is not used for booting.
S3C6400X RISC MICROPROCESSOR
DESCRIPTION
Related IPs
Camera and JPEG
Display
POST
MFC
HSMMC and OTG
Host I/F
DMA
Security
ARM Core Instruction
ARM Core Data
ARM Core DMA
CFCON
DESCRIPTION
RESET VALUE
0x0000_0000
0000
RESET VALUE
0x0000_00
0
0
0
0
0
XOM dependent
XOM dependent