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DISPLAY CONTROLLER
INDE
2
X\Bit
4
Pos.
00H
01H
.......
FFH
Num
ber
of
VD
Palette Read/Write
It is prohibited to access Palette memory during the ACTIVE status of the VSTATUS (vertical status) register.
When you execute to do Read/Write operation on the palette, VSTATUS register must be checked.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-18
Specifications and information herein are subject to change without notice.
Table 14-2. 16BPP(A:5:5:5) Palette Data Format
2
2
2
2
1
1
1
1
3
2
1
0
9
8
7
6
- A
-
-
-
-
-
-
-
- A
-
-
-
-
-
-
-
- ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
-
-
-
-
-
-
-
- A
-
-
-
-
-
-
-
- -
-
-
-
-
-
-
-
1
1
1
1
1
1
9 8 7 6 5 4 3 2 1 0
5
4
3
2
1
0
R
R
R
R
R
G
G
E
4
3
2
1
0
4
3
N
R
R
R
R
R
G
G
E
4
3
2
1
0
4
3
N
R
R
R
R
R
G
G
E
4
3
2
1
0
4
3
N
2
2
2
2
1
1
1
3
2
1
0
9
5
4
S3C6400X RISC MICROPROCESSOR
G
G
G
B
B
B
B
B
2
1
0
4
3
2
1
0
G
G
G
B
B
B
B
B
2
1
0
4
3
2
1
0
G
G
G
B
B
B
B
B
2
1
0
4
3
2
1
0
1
1
1
7 6 5 4 3
3
2
1
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