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USB2.0 HS OTG
HCTSIZ10
0x650
HCDMA10
0x654
HCCHAR11
0x660
HCSPLT11
0x664
HCINT11
0x668
HCINTMSK11
0x66C
HCTSIZ11
0x670
HCDMA11
0x674
HCCHAR12
0x680
HCSPLT12
0x684
HCINT12
0x688
HCINTMSK12
0x68C
HCTSIZ12
0x690
HCDMA12
0x694
HCCHAR13
0x6A0
HCSPLT13
0x6A4
HCINT13
0x6A8
HCINTMSK13
0x6AC
HCTSIZ13
0x6B0
HCDMA13
0x6B4
HCCHAR14
0x6C0
HCSPLT14
0x6C4
HCINT14
0x6C8
HCINTMSK14
0x6CC
HCTSIZ14
0x6D0
HCDMA14
0x6D4
HCCHAR15
0x6E0
HCSPLT15
0x6E4
HCINT15
0x6E8
HCINTMSK15
0x6EC
HCTSIZ15
0x6F0
HCDMA15
0x6F4
Device Global Registers
DCFG
0x800
DCTL
0x804
DSTS
0x808
DIEPMSK
0x810
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-10
Specifications and information herein are subject to change without notice.
R/W
Host Channel 10 Transfer Size Register
R/W
Host Channel 10 DMA Address Register
R/W
Host Channel 11 Characteristics Register
R/W
Host Channel 11 Spilt Control Register
R/W
Host Channel 11 Interrupt Register
R/W
Host Channel 11 Interrupt Mask Register
R/W
Host Channel 11 Transfer Size Register
R/W
Host Channel 11 DMA Address Register
R/W
Host Channel 12 Characteristics Register
R/W
Host Channel 12 Spilt Control Register
R/W
Host Channel 12 Interrupt Register
R/W
Host Channel 12 Interrupt Mask Register
R/W
Host Channel 12 Transfer Size Register
R/W
Host Channel 12 DMA Address Register
R/W
Host Channel 13 Characteristics Register
R/W
Host Channel 13 Spilt Control Register
R/W
Host Channel 13 Interrupt Register
R/W
Host Channel 13 Interrupt Mask Register
R/W
Host Channel 13 Transfer Size Register
R/W
Host Channel 13 DMA Address Register
R/W
Host Channel 14 Characteristics Register
R/W
Host Channel 14 Spilt Control Register
R/W
Host Channel 14 Interrupt Register
R/W
Host Channel 14 Interrupt Mask Register
R/W
Host Channel 14 Transfer Size Register
R/W
Host Channel 14 DMA Address Register
R/W
Host Channel 15 Characteristics Register
R/W
Host Channel 15 Spilt Control Register
R/W
Host Channel 15 Interrupt Register
R/W
Host Channel 15 Interrupt Mask Register
R/W
Host Channel 15 Transfer Size Register
R/W
Host Channel 15 DMA Address Register
Device Mode Registers
R/W
Device Configuration Register
R/W
Device Control Register
R
Device Status Register
R/W
Device IN Endpoint Common Interrupt Mask
S3C6400X RISC MICROPROCESSOR
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0020_0000
0x0000_0000
0x0000_0002
0x0000_0000
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