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S3C6400 RISC MICROPROCESSOR
Interrupt error status register, DMACIntErrorStatus
The DMACIntErrorStatus register is read-only register and indicates the status of the error request after masking.
This register must be used in conjunction with the DMACIntStatus register if the combined interrupt request,
DMACINTCOMBINE, is used to request interrupts.
If the DMACINTERROR interrupt request is used only the DMACIntErrorStatus register needs to be read.
Table 11-5 shows the bit assignment of the DMACIntErrorStatus register.
DMACIntErrorStatus
IntErrorStatus
Interrupt error clear register, DMACIntErrClr
The DMACIntErrClr register is a write-only register and is used to clear the error interrupt requests. When writing to
this register, each data bit that is HIGH causes the corresponding bit in the status register to be cleared. Data bits
that are LOW have no effect on the corresponding bit in the register.
Table 11-6 shows the bit assignment of the DMACIntErrClr register.
DMACIntErrClr
IntErrClr
Raw interrupt terminal counter status register, DMACRawIntTCStatus
The DMACRawIntTCStatus register is read-only. It indicates which DMA channels are requesting a transfer
complete (terminal count interrupt) prior to masking. A HIGH bit indicates that the terminal count interrupt request is
active prior to masking.
Table 11-7 shows the bit assignment of the DMACRawIntTCStatus register.
DMACRawIntTCStatus
RawIntTCStatus
Table 11-5. Bit Assignment of DMACIntErrorStatus register
Bits
Type
Function
[7:0]
R
Interrupt error status
Table 11-6. Bit Assignment of DMACIntErrClr register
Bits
Type
Function
[7:0]
W
Interrupt error clear
Table 11-7. Bit Assignment of DMACRawIntTCStatus register
Bits
Type
Function
[7:0]
R
Status of the terminal count interrupt prior to masking
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DMA
11-17
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