Samsung S3C6400X User Manual page 85

SYSTEM CONTROLLER
Memory controller status register
Memory controller status registers should be initialized by software except MEM_CFG_STAT.
REGISTER
MEM_SYS_CFG 0x7E00_F120
QOS_OVERRIDE0 0x7E00_F124
QOS_OVERRIDE1 0x7E00_F128
MEM_CFG_STAT 0x7E00_F12C
MEM_SYS_CFG BIT
RESERVED [31:15] RESERVED
INDEP_CF [14]
RESERVED [13]
BUS_WIDTH [12]
EBI_PRI [11]
EBI_FIX_PRI [10:8]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-40
Specifications and information herein are subject to change without notice.
ADDRESS R/W
R/W
R/W
R/W
R
Use CF interface independently.
0 = Use memory port 0 shared by EBI.
1 = Use independent CF interface.
RESERVED
Select initial state of SROMC CS0 memory bus width.
0 = 8-bit data width.
1 = 16-bit data width.
If NOR booting (OM[4:1] = 0101) is selected, this setting is
ignored and 16-bit data width is selected.
Even this bit is set to 0 or 1, this selects only reset value of
DataWidth0 of SROM_BW SFR in SROMC. Bus width of CS0
for SROMC follows DataWidth0 setting.
Set EBI priority scheme.
0 = Fixed priority scheme.
1 = Circular priority scheme.
Set EBI fixed priority setting.
Highest
DMC0 – SROMC - OneNANDC CS0 - OneNANDC CS1 –
0,6,7
NFCON – CFCON
DMC0 – OneNANDC CS0 – OneNANDC CS1 – SROMC –
1
NFCON – CFCON
DMC0 - OneNANDC CS1 – NFCON – SROMC -
2
OneNANDC CS0 – CFCON
DMC0 – NFCON – SROMC - OneNANDC CS0 -
3
OneNANDC CS1 – CFCON
DMC0 – CFCON – SROMC - OneNANDC CS0 -
4
OneNANDC CS1 – NFCON
DESCRIPTION
Memory Subsystem configuration register
DMC0 QOS Override register
DMC1 QOS Override register
Memory Subsystem setup status register
DESCRIPTION
<->
S3C6400X RISC MICROPROCESSOR
RESET VALUE
0x0000_0080
0x0000_0000
0x0000_0000
0x0000_0000
RESET VALUE
0x0000_0
Lowest
000
0
0
0
0