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Section 2 CPU
2.5.2
Program Counter (PC)
PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is two bytes (one word) or a multiple of two bytes, so the least
significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
2.5.3
Condition-Code Register (CCR)
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
7
I
6
UI
Rev.2.00 Jun. 28, 2007 Page 26 of 666
REJ09B0311-0200
SP (ER7)
Figure 2.11 Stack
Initial
Value
R/W
1
R/W
Undefined R/W
Description
Interrupt Mask Bit
Masks interrupts when set to 1. This bit is set to 1 at the
start of an exception-handling sequence.
User Bit or Interrupt Mask Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit can
also be used as an interrupt mask bit.
Free area
Stack area
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