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17.4.5
Data Transmission/Reception Through the LPC Interface
As shown in table 17.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to
be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the
SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception
shown in figures 17.3 to 17.5 to be made from the LPC interface. Table 17.7 shows the
correspondence between LPC interface I/O address and access to the SCIF registers. For details of
the LPC interface settings, see section 20, LPC interface (LPC).
Table 17.7 Correspondence Between LPC Interface I/O Address and the SCIF Registers
LPC Interface I/O Address
Bits 15 to 3
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
R/W
Condition
R
FLCR[7] = 0
W
FLCR[7] = 0
R/W
FLCR[7] = 1
R/W
FLCR[7] = 0
R/W
FLCR[7] = 1
R
W
R/W
R/W
R
R
R/W
Rev. 1.00 Apr. 28, 2008 Page 525 of 994
SCIF
Register
FRBR
FTHR
FDLL
FIER
FDLH
FIIR
FFCR
FLCR
FMCR
FLSR
FMSR
FSCR
REJ09B0452-0100
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