Data Transmission (Asynchronous Mode); Figure 14.6 Example Of Operation In Transmission In Asynchronous Mode (Example With 8-Bit Data, Parity, One Stop Bit) - Renesas H8S Series Hardware Manual

14.4.5

Data Transmission (Asynchronous Mode)

Figure 14.6 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.
Start
1
bit
0 D0
TDRE
TEND
TXI interrupt Data written to TDR and
request generated TDRE flag cleared to 0 in
TXI interrupt service routine
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
Data Parity Stop
bit bit
D1 D7 0/1
TXI interrupt
request generated
1 frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Section 14 Serial Communication Interface (SCI)
Start Data
bit
1 0 D0 D1
Rev. 6.00 Mar 15, 2006 page 343 of 570
Parity Stop
1
bit bit
Idle state
D7 0/1 1
(mark state)
TEI interrupt
request generated
REJ09B0211-0600