Input Data Registers 1 To 4 (Idr1 To Idr4); Output Data Registers 1 To 4 (Odr1 To Odr4) - Renesas H8S/2100 Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

• Host select register

Bits 15 to 3 in LADR4

When channel 4 is used, the content of LADR4 must be set so that the addresses for

channels 1, 2, 3 and SCIF are different.

Input Data Registers 1 to 4 (IDR1 to IDR4)

IDR1 to IDR4 are 8-bit read-only registers for the slave (this LSI), and 8-bit write-only registers

for the host. The registers selected from the host according to the I/O address are shown in the

following table. Data transferred in an LPC I/O write cycle is written to the selected register. The

value of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written

information is a command or data. The initial values of IDR1 to IDR4 are H'00.

Bits 15 to 4

Bits 15 to 4

Bits 15 to 4

ODR1 to ODR4 are 8-bit readable/writable registers for the slave (this LSI), and 8-bit read-only

registers for the host. The registers selected from the host according to the I/O address are shown

in the following table. In an LPC I/O read cycle, the data in the selected register is transferred to

the host. The initial values of ODR1 to ODR4 are H'00.

Bits 15 to 4

Bits 15 to 4

Bits 1 and 0

Bits 1 and 0 in LADR4

Rev. 1.00 Apr. 28, 2008 Page 637 of 994

Section 20 LPC Interface (LPC)

Host Select Register

IDR4 write (data)

IDR4 write (command)

Host Register Selection

IDRn write, C/Dn ← 0

IDRn write, C/Dn ← 1

Host Register Selection

REJ09B0452-0100

H8s/2117r series R4f2117r