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Bits 15 to 4
0000 0000 0110
0000 0000 0110
• STR1
Bit
Bit Name
7
DBU17
6
DBU16
5
DBU15
4
DBU14
3
C/D1
2
DBU12
1
IBF1
0
OBF1
Note:
Only 0 can be written to clear the flag.
*
Rev. 1.00, 05/04, page 382 of 544
I/O Address
Bit 3
Bit 2
Bit 1
0
1
0
0
1
1
R/W
Initial
Value Slave Host Description
0
R/W
R
0
R/W
R
0
R/W
R
0
R/W
R
0
R
R
0
R/W
R
0
R
R
0
R/(W)* R
Transfer
Cycle
Bit 0
0
I/O read
0
I/O read
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor
(this LSI). IBF is cleared to 0 when the slave processor
reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Host Register Selection
STR1 read
STR2 read
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