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20.3.3
Host Interface Control Register 4 (HICR4)
HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface
slave (this LSI).
Initial
Bit
Bit Name
Value
7
0
6
LPC4E
0
5
IBFIE4
0
4 to 0
All 0
R/W
Slave Host Description
R/W
Reserved
The initial value bit should not be changed.
R/W
LPC Enable 4
0: LPC channel 4 is disabled
For IDR4, ODR4, and STR4, address (LADR4)
match is not occurred.
1: LPC channel 4 enabled
R/W
IDR4 Receive Completion Interrupt Enable
Enables or disables IBFI4 interrupt to the slave (this
LSI).
0: Input data register (IDR4) receive complete
interrupt requests disabled
1: Input data register (IDR4) receive complete
interrupt requests enabled
R/W
Reserved
The initial value should not be changed.
Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 629 of 994
REJ09B0452-0100
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