Host Interface Control Registers 0 And 1 (Hicr0, Hicr1) - Renesas H8S/2111B Hardware Manual

Bit Bit Name
2 PMEE
1 LSMIE
0 LSCIE
[Legend]
X: Don't care
R/W
Initial
Value Slave Host Description
0 R/W —
0 R/W —
0 R/W —
PME output Enable
Controls PME output in combination with the PMEB bit
in HICR1. PME pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to V
When the PME output function is used, the DDR bit for
P80 must not be set to 1.
PMEE PMEB
0 x: PME output disabled, other function of
pin is enabled
0: PME output enabled, PME pin output
1
goes to 0 level
1: PME output enabled, PME pin output is
1
high-impedance
LSMI output Enable
Controls LSMI output in combination with the LSMIB bit
in HICR1. LSMI pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to V
When the LSMI output function is used, the DDR bit for
PB0 must not be set to 1.
LSMIE LSMIB
0 x: LSMI output disabled, other function of
pin is enabled
0: LSMI output enabled, LSMI pin output
1
goes to 0 level
1: LSMI output enabled, LSMI pin output is
1
high-impedance
LSCI output Enable
Controls LSCI output in combination with the LSCIB bit
in HICR1. LSCI pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to V
When the LSCI output function is used, the DDR bit for
PB1 must not be set to 1.
LSCIE LSCIB
0 x: LSCI output disabled, other function of
pin is enabled
1 0: LSCI output enabled, LSCI pin output
goes to 0 level
1 1: LSCI output enabled, LSCI pin output is
high-impedance
Rev. 1.00, 05/04, page 373 of 544
CC
CC
CC