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[A]
Address space ......................................................... 58
Application system example .................................... 18
[B]
BBR ....................................................................... 118
BC15 to BC0.......................................................... 156
BCU ......................................................................... 74
BCUNCH.................................................................. 39
BCU-related register setting examples .................... 91
BEC ......................................................................... 87
BEn0 ........................................................................ 87
BHC ......................................................................... 90
BHn0........................................................................ 90
BHn1........................................................................ 90
Block transfer mode............................................... 171
BPC ................................................................. 85, 121
BSC ......................................................................... 86
BSn1, BSn0 ............................................................. 86
BUNRI...................................................................... 44
BUNRIOUT .............................................................. 44
Bus size configuration register................................. 86
Bus size setting function .......................................... 86
[C]
Cache configuration................................................. 90
Cache configuration register.................................... 90
CGREL .................................................................... 35
CH3 to CH0 ........................................................... 160
Chip area select control register 0 ........................... 77
Chip area select control register 1 ........................... 78
Clock control .......................................................... 144
Command register ................................................. 139
CPU ......................................................................... 51
CSC0 ....................................................................... 77
CSC1 ....................................................................... 78
CSn3 to CSn0.................................................... 77, 78
CTBP ....................................................................... 55
CTPC ....................................................................... 55
CTPSW.................................................................... 55
CY............................................................................ 57
[D]
DA15 to DA0.......................................................... 155
APPENDIX B INDEX
DA27 to DA16 ........................................................154
DAD1, DAD0 ..........................................................158
DADC0 to DADC3 ..................................................157
Data area .................................................................60
Data transfer using VSB...........................................94
DBB15 to DBB0........................................................41
DBC0 to DBC3 .......................................................156
DBI5 to DBI0 ............................................................41
DBO14 to DBO0.......................................................41
DBPC .......................................................................55
DBPSW ....................................................................55
DCHC0 to DCHC3..................................................159
DCNMI2 to DCNMI0 .................................................36
DCRESZ...................................................................34
DCSTOPZ ................................................................35
DDA0 to DDA3 .......................................................154
DDIS.......................................................................160
Debug function .......................................................242
DMA addressing control registers 0 to 3 ................157
DMA bus state........................................................163
DMA channel control registers 0 to 3 .....................159
DMA channel priorities ...........................................151
DMA destination address registers 0 to 3 ..............154
DMA disable status register ...................................160
DMA restart register ...............................................161
DMA source address registers 0 to 3 .....................152
DMA transfer count registers 0 to 3........................156
DMA transfer start factors ......................................175
DMA transfer timing examples ...............................180
DMAC.....................................................................149
DMAC bus cycle state transitions ..........................165
DMACTV3 to DMACTV0 ..........................................36
DMARQ3 to DMARQ0..............................................36
DMTCO3 to DMTCO0 ..............................................36
DRST......................................................................161
DS1, DS0 ...............................................................157
DSA0 to DSA3........................................................152
[E]
ECR....................................................................55, 56
EICC.........................................................................56
EIPC .........................................................................55
EIPSW......................................................................55
EN3 to EN0 ............................................................161
Preliminary User's Manual A14874EJ3V0UM
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