Timer I/O Control Register (Tior) - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.3

Timer I/O Control Register (TIOR)

TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one
each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin
should be set to 0 and 1, respectively. For details, see section 8, I/O Ports.
Note: The H8SX/1527 does not include TIOR_4 and TIOR_5.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial Value
R/W
• TIORL_0, TORL_3
Bit
Bit Name
Initial Value
R/W
Rev. 3.00 Mar. 14, 2006 Page 272 of 804
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7 6
IOB3 IOB2 IOB1
0 0
R/W R/W R/W
7 6
IOD3 IOD2 IOD1
0 0
R/W R/W R/W
5 4 3
IOB0 IOA3
0 0 0
R/W R/W
5 4 3
IOD0 IOC3
0 0 0
R/W R/W
2 1
IOA2 IOA1 IOA0
0 0
R/W R/W R/W
2 1
IOC2 IOC1 IOC0
0 0
R/W R/W R/W
0
0
0
0